coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by Yidi Lin (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, cong yang, ot_hao.han(a)mediatek.com. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/geralt/panel.c: https://review.coreboot.org/c/coreboot/+/78957/comment/0001a9f2_b23dc9e6 : PS11, Line 72: mdelay(10); > This delay is not needed for i2c and should be required by the panel. We can move `mtk_i2c_bus_init` to the beginning to make power-on sequences more clear. ``` mtk_i2c_bus_init(cfg->i2c_bus, I2C_SPEED_FAST); /* Enable VM18V */ mainboard_enable_regulator(MTK_REGULATOR_VDD18, true); mdelay(1); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 11 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 07:36:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Marek Maślanka (Code Review) 12 Jan '24

12 Jan '24

Marek Maślanka has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... soc/intel/common/block: Add support for watchdog Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka(a)google.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/include/intelpch/smbus.h 4 files changed, 133 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79909/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index eed1530..8d736f4 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -16,6 +16,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pmclib.h> #include <intelblocks/sgx.h> +#include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -389,3 +390,110 @@ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) sgx_fill_ssdt(); } + +unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + wdat->pci_segment = 0xff; + wdat->pci_bus = 0xff; + wdat->pci_device = 0xff; + wdat->pci_function = 0xff; + + wdat->timer_period = tco_get_timer_period(); + wdat->min_count = 1; + wdat->max_count = tco_get_timer_max_value() * tco_get_timer_period() / 1000; + wdat->flags = ACPI_WDAT_FLAG_ENABLED; + wdat->entries = 0; + + // write countdown + acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_SET_COUNTDOWN; + entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = 0x3ff; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO_TMR; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + // get boot status + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_GET_STATUS; + entry->instruction = ACPI_WDAT_READ_VALUE; + entry->mask = 0x01; + entry->value = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_BYTE; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO_MESSAGE1; + entry->register_region.bit_offset = 1; + + // set boot status + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_SET_STATUS; + entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = 0x02; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_BYTE; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO_MESSAGE1; + + // get running status + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_GET_RUNNING_STATE; + entry->instruction = ACPI_WDAT_READ_VALUE; + entry->mask = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO1_CNT; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + entry->register_region.bit_offset = 11; + + // set running status + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_SET_RUNNING_STATE; + entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO1_CNT; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + entry->register_region.bit_offset = 11; + + // set stopped status + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_SET_STOPPED_STATE; + entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = 0x01; + entry->value = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO1_CNT; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + entry->register_region.bit_offset = 11; + + // ping + entry++; + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + wdat->entries++; + + entry->action = ACPI_WDAT_RESET; + entry->instruction = ACPI_WDAT_WRITE_VALUE; + entry->mask = 0x01; + entry->value = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = TCO_BASE_ADDRESS + TCO_RLD; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return current + (wdat->entries * sizeof(acpi_wdat_entry_t)); +} diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 35cbfb1..2eb18b1 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -20,4 +20,9 @@ uint16_t tco_read_reg(uint16_t tco_reg); void tco_write_reg(uint16_t tco_reg, uint16_t value); +/* Get TCO timer period in miliseconds */ +u32 tco_get_timer_period(void); +/* Get the maximum time value for the TCO timer */ +u32 tco_get_timer_max_value(void); + #endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1f1a85c..c3ac3c0 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -22,6 +22,9 @@ #define TCO_BASE_EN (1 << 8) #define TCO_BASE_LOCK (1 << 0) +#define TCO_TMR_MAX_VALUE 1023 +#define TCO_TMR_PERIOD_MS 600 + /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) { @@ -73,6 +76,10 @@ tco2_sts = tco_read_reg(TCO2_STS); tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO); + if (CONFIG(ACPI_WDAT_WDT)) { + tco_write_reg(TCO_MESSAGE1, tco2_sts & TCO2_STS_SECOND_TO); + } + return (tco2_sts << 16) | tco1_sts; } @@ -137,3 +144,13 @@ if (CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)) tco_intruder_smi_enable(); } + +u32 tco_get_timer_period(void) +{ + return TCO_TMR_PERIOD_MS; +} + +u32 tco_get_timer_max_value(void) +{ + return TCO_TMR_MAX_VALUE; +} diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h index 78b7953..4c50a70 100644 --- a/src/soc/intel/common/pch/include/intelpch/smbus.h +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -4,6 +4,7 @@ #define _INTELPCH_SMBUS_H_ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO_RLD 0x00 #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 @@ -16,7 +17,8 @@ #define TCO_INTRD_SEL_MASK (3 << 1) #define TCO_INTRD_SEL_SMI (1 << 2) #define TCO_INTRD_SEL_INT (1 << 1) - +#define TCO_MESSAGE1 0x0C +#define TCO_TMR 0x12 /* * Default slave address value for PCH. This value is set to match default * value set by hardware. It is useful since PCH is able to respond even -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 1 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Support multiple PCI segment groups
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Nill Ge, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Support multiple PCI segment groups ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: TODO: cxl_fill_srat -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 07:29:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri
by ot_hao.han＠mediatek.com (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, Yidi Lin, cong yang. ot_hao.han(a)mediatek.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78957?usp=email ) Change subject: mb/google/geralt: Enable BOE_NV110WUM_L60 panel for Ciri ...................................................................... Patch Set 11: Code-Review+1 (1 comment) File src/mainboard/google/geralt/panel.c: https://review.coreboot.org/c/coreboot/+/78957/comment/ea5692c5_1b110ce6 : PS11, Line 72: mdelay(10); > No, I thought it was required by MT8188's I2C according to the comment in CB72749. […] This delay is not needed for i2c and should be required by the panel. -- To view, visit https://review.coreboot.org/c/coreboot/+/78957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a04f062f81c543d38716d7ff185b5633c1aa3a9 Gerrit-Change-Number: 78957 Gerrit-PatchSet: 11 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: ot_hao.han(a)mediatek.com <ot_hao.han(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 07:26:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/ifdtool: Enable Read Access for SPI device expansion 2 region
by Subrata Banik (Code Review) 12 Jan '24

12 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79902?usp=email ) Change subject: util/ifdtool: Enable Read Access for SPI device expansion 2 region ...................................................................... util/ifdtool: Enable Read Access for SPI device expansion 2 region As per Intel Meteor Lake SPI programming doc, the BIOS region should have a read access enabled for device expansion 2 region (aka region 9). This patch ensures that BIOS region is able to read the device expansion 2 region for Intel Meteor Lake platform as known as SPI padding region. BUG=b:274356894 BRANCH=firmware-rex-15709.B TEST=Able to flash screebo AP FW image using flashrom on DUT. Without this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.67-09255-ge8ae3115f8b0 (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... Transaction error between offset 0x0072f000 and 0x0072f03f (= 0x0072f000 + 63)! read_flash: failed to read (0x72f000..0x7fffff). Read operation failed! FAILED. FAILED With this patch: > flashrom -p internal -r /tmp/bios.rom flashrom 1.4.0-devel on Linux 6.1.68-09294-g001fdda5287d (x86_64) ... ... Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific) on internal. Reading flash... done. SUCCESS Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79902 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M util/ifdtool/ifdtool.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Reka Norman: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 99a83e5..191b321 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1451,6 +1451,10 @@ fmba->flmstr5 |= (1 << REGION_EC) << rd_shift; fmba->flmstr5 |= (1 << REGION_EC) << wr_shift; } + if (check_region(frba, REGION_DEV_EXP2)) { + /* BIOS can read SPI device expansion 2 region. */ + fmba->flmstr1 |= (1 << REGION_DEV_EXP2) << rd_shift; + } break; case PLATFORM_DNV: case PLATFORM_WBG: -- To view, visit https://review.coreboot.org/c/coreboot/+/79902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Gerrit-Change-Number: 79902 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: util/ifdtool: Enable Read Access for SPI device expansion 2 region
by Eric Lai (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Kane Chen, Kun Liu, Stefan Reinauer, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79902?usp=email ) Change subject: util/ifdtool: Enable Read Access for SPI device expansion 2 region ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79902?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8 Gerrit-Change-Number: 79902 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 06:53:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/smbios: rename segment group parameter of smbios_write_type41
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79926?usp=email ) Change subject: lib/smbios: rename segment group parameter of smbios_write_type41 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e Gerrit-Change-Number: 79926 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Jan 2024 06:35:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib/smbios: add segment_group parameter to smbios_write_type9
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79925?usp=email ) Change subject: lib/smbios: add segment_group parameter to smbios_write_type9 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Gerrit-Change-Number: 79925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 06:35:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/data_fabric/domain: write _SEG method in SSDT
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79924?usp=email ) Change subject: soc/amd/common/data_fabric/domain: write _SEG method in SSDT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a Gerrit-Change-Number: 79924 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Jan 2024 06:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: acpi/acpigen: add acpigen_write_SEG for segment group number method
by Patrick Rudolph (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79923?usp=email ) Change subject: acpi/acpigen: add acpigen_write_SEG for segment group number method ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Gerrit-Change-Number: 79923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 12 Jan 2024 06:34:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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