coreboot-gerrit January 2024

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[M] Change in coreboot[main]: soc/intel/jasperlake: Drop redundant PcieRpEnable
by Nico Huber (Code Review) 12 Jan '24

12 Jan '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79919?usp=email ) Change subject: soc/intel/jasperlake: Drop redundant PcieRpEnable ...................................................................... soc/intel/jasperlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Note: Jenkins will fail because somebody has to go through all the dts. Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/include/soc/pcie.h A src/soc/intel/jasperlake/pcie_rp.c M src/soc/intel/jasperlake/romstage/fsp_params.c 7 files changed, 27 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/79919/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 957ab1d..59d69dc 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,11 +63,6 @@ register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" - # PCIe port 1 for M.2 E-key WLAN - # Enable Root Port 4(x4) for NVMe - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable ClkReqDetect 1 for WLAN # Enable ClkReqDetect 4 for NVMe register "PcieRpClkReqDetect[1]" = "1" @@ -469,14 +464,8 @@ device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - WLAN - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.1 on end # PCI Express Port 2 - M.2 E-key WLAN device pci 1c.4 on end # PCI Express Port 5 - NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 31ea865..1377fff 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += espi.c romstage-y += gpio.c romstage-y += meminit.c +romstage-y += pcie_rp.c romstage-y += reset.c ramstage-y += acpi.c @@ -35,6 +36,7 @@ ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += systemagent.c diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index c049163f..d96244b 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -14,14 +14,10 @@ #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> -static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 66ad223..af7ee54 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -146,7 +146,6 @@ bool PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/jasperlake/include/soc/pcie.h b/src/soc/intel/jasperlake/include/soc/pcie.h new file mode 100644 index 0000000..17710cc --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_JASPERLAKE_PCIE_H__ +#define __SOC_JASPERLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +extern const struct pcie_rp_group pch_rp_groups[]; + +#endif /* __SOC_JASPERLAKE_PCIE_H__ */ diff --git a/src/soc/intel/jasperlake/pcie_rp.c b/src/soc/intel/jasperlake/pcie_rp.c new file mode 100644 index 0000000..844cc54 --- /dev/null +++ b/src/soc/intel/jasperlake/pcie_rp.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +const struct pcie_rp_group pch_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 43a8c70..0132906 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -5,8 +5,10 @@ #include <device/device.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -14,7 +16,6 @@ const struct soc_intel_jasperlake_config *config) { unsigned int i; - uint32_t mask = 0; /* * If IGD is enabled, set IGD stolen size to 60MB. @@ -61,13 +62,7 @@ } } - /* PCIe root port configuration */ - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups); FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage); FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq); -- To view, visit https://review.coreboot.org/c/coreboot/+/79919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Gerrit-Change-Number: 79919 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/cannonlake: Drop redundant PcieRpEnable
by Nico Huber (Code Review) 12 Jan '24

12 Jan '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79918?usp=email ) Change subject: soc/intel/cannonlake: Drop redundant PcieRpEnable ...................................................................... soc/intel/cannonlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Note: Jenkins will fail because somebody has to go through all the dts. Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/pcie.h A src/soc/intel/cannonlake/pcie_rp.c M src/soc/intel/cannonlake/romstage/fsp_params.c 11 files changed, 63 insertions(+), 200 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/79918/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb index 2269d74..6f0c667 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb @@ -44,31 +44,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" - register "PcieRpEnable[10]" = "1" - register "PcieRpEnable[11]" = "1" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "0" - register "PcieRpEnable[17]" = "0" - register "PcieRpEnable[18]" = "0" - register "PcieRpEnable[19]" = "0" - register "PcieRpEnable[20]" = "0" - register "PcieRpEnable[21]" = "0" - register "PcieRpEnable[22]" = "0" - register "PcieRpEnable[23]" = "0" - register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" @@ -97,30 +72,15 @@ device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + device ref pcie_rp5 on # x1 SLOT2/LAN register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 off end # PCI Express Port 17 - device pci 1b.1 off end # PCI Express Port 18 - device pci 1b.2 off end # PCI Express Port 19 - device pci 1b.3 off end # PCI Express Port 20 - device pci 1b.4 off end # PCI Express Port 21 - device pci 1b.5 off end # PCI Express Port 22 - device pci 1b.6 off end # PCI Express Port 23 - device pci 1b.7 off end # PCI Express Port 24 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb index b6bf5a8..567e7ef 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb @@ -42,31 +42,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieRpEnable[16]" = "1" - register "PcieRpEnable[17]" = "1" - register "PcieRpEnable[18]" = "1" - register "PcieRpEnable[19]" = "1" - register "PcieRpEnable[20]" = "1" - register "PcieRpEnable[21]" = "1" - register "PcieRpEnable[22]" = "1" - register "PcieRpEnable[23]" = "1" - register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" @@ -105,38 +80,28 @@ device pci 19.1 off end # I2C #5 (Not available on PCH-H) device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 + device ref pcie_rp1 on register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1 + device ref pcie_rp9 on # x4 SLOT 1 register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on # PCI Express Port 17 + device ref pcie_rp17 on register "PcieRpSlotImplemented[16]" = "1" end - device pci 1b.1 on # PCI Express Port 18 + device ref pcie_rp18 on register "PcieRpSlotImplemented[17]" = "1" end - device pci 1b.2 on # PCI Express Port 19 + device ref pcie_rp19 on register "PcieRpSlotImplemented[18]" = "1" end - device pci 1b.3 on # PCI Express Port 20 + device ref pcie_rp20 on register "PcieRpSlotImplemented[19]" = "1" end - device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2 + device ref pcie_rp21 on # x4 SLOT 2 register "PcieRpSlotImplemented[20]" = "1" end device pci 1e.1 off end # UART #1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb index ce46c63..367026f 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb @@ -5,23 +5,6 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" @@ -82,25 +65,15 @@ device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + device ref pcie_rp5 on # x1 SLOT2/LAN register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb index b9fe423..1bf603a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb @@ -43,23 +43,6 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" @@ -94,25 +77,15 @@ device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + device ref pcie_rp5 on # x1 SLOT2/LAN register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 device pci 1e.1 off end # UART #1 device pci 1f.6 on end # GbE end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb index 9c08023..415eb46 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb @@ -28,23 +28,6 @@ register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "0" - register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "0" - register "PcieRpEnable[10]" = "0" - register "PcieRpEnable[11]" = "0" - register "PcieRpEnable[12]" = "0" - register "PcieRpEnable[13]" = "0" - register "PcieRpEnable[14]" = "0" - register "PcieRpEnable[15]" = "0" - register "PcieClkSrcUsage[0]" = "1" register "PcieClkSrcUsage[1]" = "8" register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" @@ -78,25 +61,15 @@ device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + device ref pcie_rp1 on # x4 SLOT1 register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + device ref pcie_rp5 on # x1 SLOT2/LAN register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 device pci 1e.1 off end # UART #1 device pci 1f.6 on end # GbE end diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 5ae0099..96c0207 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -21,6 +21,7 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += lpc.c +romstage-y += pcie_rp.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -39,6 +40,7 @@ ramstage-y += lpc.c ramstage-y += nhlt.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-y += reset.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index a1ba17e..06ef7e5 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -14,23 +14,11 @@ #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include "chip.h" -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - -static const struct pcie_rp_group pch_h_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -152,10 +140,7 @@ soc_gpio_pm_configuration(); /* swap enabled PCI ports in device tree if needed */ - if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) - pcie_rp_update_devicetree(pch_h_rp_groups); - else - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } static void cpu_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 994f2ae..69a19b5 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -167,7 +167,6 @@ bool PchHdaAudioLinkSndw4; /* PCIe Root Ports */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ diff --git a/src/soc/intel/cannonlake/include/soc/pcie.h b/src/soc/intel/cannonlake/include/soc/pcie.h new file mode 100644 index 0000000..1ae524d --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_CANNONLAKE_PCIE_H__ +#define __SOC_CANNONLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); + +#endif /* __SOC_CANNONLAKE_PCIE_H__ */ diff --git a/src/soc/intel/cannonlake/pcie_rp.c b/src/soc/intel/cannonlake/pcie_rp.c new file mode 100644 index 0000000..4d37841 --- /dev/null +++ b/src/soc/intel/cannonlake/pcie_rp.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) + return pch_h_rp_groups; + + return pch_lp_rp_groups; +} diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 737e7c3..c25921f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -6,11 +6,13 @@ #include <console/console.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/pmclib.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <types.h> @@ -24,7 +26,6 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig; unsigned int i; - uint32_t mask = 0; m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); @@ -52,11 +53,7 @@ m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->RMT; - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) -- To view, visit https://review.coreboot.org/c/coreboot/+/79918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9 Gerrit-Change-Number: 79918 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable
by Nico Huber (Code Review) 12 Jan '24

12 Jan '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email ) Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ...................................................................... soc/intel/skylake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infracture instead. Note: Jenkins will fail because somebody has to go through all the dts. Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h A src/soc/intel/skylake/include/soc/pcie.h A src/soc/intel/skylake/pcie_rp.c M src/soc/intel/skylake/romstage/fsp_params.c 10 files changed, 53 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/79917/1 diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b580e76..684c131 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -7,37 +7,31 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enable PCIE slot - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 # RP6, uses CLK SRC 1 register "PcieRpClkSrcNumber[5]" = "1" - register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 # RP7, uses CLK SRC 2 register "PcieRpClkSrcNumber[6]" = "2" - register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 # RP8, uses CLK SRC 3 register "PcieRpClkSrcNumber[7]" = "3" - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 # RP9, uses CLK SRC 4 register "PcieRpClkSrcNumber[8]" = "4" - register "PcieRpEnable[13]" = "1" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 # RP14, uses CLK SRC 5 register "PcieRpClkSrcNumber[13]" = "5" - register "PcieRpEnable[16]" = "1" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 # RP17, uses CLK SRC 7 @@ -112,6 +106,12 @@ device ref i2c3 off end device ref sata on end device ref i2c4 off end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp14 on end + device ref pcie_rp17 on end device ref emmc off end device ref sdxc off end device ref hda on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395..ac384d7 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -38,21 +38,18 @@ # Enable Root ports. # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" # RP1, uses CLK SRC 2 register "PcieRpClkSrcNumber[0]" = "2" # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" # RP5, uses CLK SRC 3 register "PcieRpClkSrcNumber[4]" = "3" # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" # RP6, uses CLK SRC 1 @@ -61,14 +58,12 @@ # PCIE Port 7 Disabled # PCIE Port 8 Disabled # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" # RP9, uses CLK SRC 5 register "PcieRpClkSrcNumber[8]" = "5" # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" # RP10, uses CLK SRC 4 diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index c5b7e94..18fe14e 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -81,13 +81,6 @@ .voltage_limit = 0 }" - # Enable Root ports. - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqSupport[3]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 2291c63..cb69194 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -77,12 +77,6 @@ .voltage_limit = 0 }" - # Enable Root port. - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[16]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqSupport[4]" = "1" @@ -168,6 +162,7 @@ device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp5 on end + device ref pcie_rp17 on end device ref emmc off end device ref sdxc off end device ref lpc_espi on diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 732a98a..5da767b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += me.c +romstage-y += pcie_rp.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -50,6 +51,7 @@ ramstage-y += lpc.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-y += reset.c diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 8df1ad3..f700c48 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -25,6 +25,7 @@ #include <soc/irq.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/usb.h> @@ -33,22 +34,6 @@ #include "chip.h" -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, - { 0 } -}; - -static const struct pcie_rp_group pch_h_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, - /* Sunrise Point PCH-H actually only has 4 ports in the - third group. But that would require a runtime check - and probing 4 non-existent ports shouldn't hurt. */ - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -180,10 +165,7 @@ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* swap enabled PCI ports in device tree if needed */ - if (CONFIG(SKYLAKE_SOC_PCH_H)) - pcie_rp_update_devicetree(pch_h_rp_groups); - else - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 3070c46..7d928b5 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -172,13 +172,6 @@ } Peg2MaxLinkWidth; /* - * Enable/Disable Root Port - * 0: Disable Root Port - * 1: Enable Root Port - */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - - /* * Enable/Disable Clk-req support for Root Port * 0: Disable Clk-Req * 1: Enable Clk-req diff --git a/src/soc/intel/skylake/include/soc/pcie.h b/src/soc/intel/skylake/include/soc/pcie.h new file mode 100644 index 0000000..4c07131 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SKYLAKE_PCIE_H__ +#define __SOC_SKYLAKE_PCIE_H__ + +#include <intelblocks/pcie_rp.h> + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); + +#endif /* __SOC_SKYLAKE_PCIE_H__ */ diff --git a/src/soc/intel/skylake/pcie_rp.c b/src/soc/intel/skylake/pcie_rp.c new file mode 100644 index 0000000..08e9c30 --- /dev/null +++ b/src/soc/intel/skylake/pcie_rp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/pcie_rp.h> +#include <soc/pci_devs.h> +#include <soc/pcie.h> + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + /* Sunrise Point PCH-H actually only has 4 ports in the + third group. But that would require a runtime check + and probing 4 non-existent ports shouldn't hurt. */ + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + if (CONFIG(SKYLAKE_SOC_PCH_H)) + return pch_h_rp_groups; + + return pch_lp_rp_groups; +} diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f24054a..ea68d94 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -4,10 +4,12 @@ #include <cpu/x86/msr.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h> @@ -74,9 +76,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { - int i; - uint32_t mask = 0; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -91,11 +90,7 @@ m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = get_valid_prmrr_size(); - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1<<i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); cpu_flex_override(m_cfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/79917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Gerrit-Change-Number: 79917 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Nico Huber, Patrick Rudolph, Tim Wawrzynczak. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79927?usp=email ) Change subject: device: Add support for multiple PCI segment groups ...................................................................... Patch Set 4: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/79927/comment/c0e8eafc_2de26bbb : PS4, Line 589: config ECAM_MMCONF_BUS_NUMBER i'll add some help text to this to point out that this configures PCI_SEGMENT_GROUP_COUNT and PCI_BUSES_PER_SEGMENT_GROUP with PCI_SEGMENT_GROUP_COUNT * PCI_BUSES_PER_SEGMENT_GROUP == CONFIG_ECAM_MMCONF_BUS_NUMBER -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 16:13:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya: Drop primus4es board
by Jakub Czapiga (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Subrata Banik. Hello Eric Lai, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79916?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: Drop primus4es board ...................................................................... mb/google/brya: Drop primus4es board Primus4es board is no longer supported thus drop it from the tree. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M Documentation/security/vboot/list_vboot.md M src/mainboard/google/brox/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/primus4es/Makefile.inc D src/mainboard/google/brya/variants/primus4es/fw_config.c D src/mainboard/google/brya/variants/primus4es/gpio.c D src/mainboard/google/brya/variants/primus4es/include/variant/ec.h D src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h D src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc D src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt D src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt D src/mainboard/google/brya/variants/primus4es/overridetree.cb D src/mainboard/google/brya/variants/primus4es/variant.c 14 files changed, 0 insertions(+), 828 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/79916/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Gerrit-Change-Number: 79916 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/google/brya: Drop primus4es board
by Jakub Czapiga (Code Review) 12 Jan '24

12 Jan '24

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79916?usp=email ) Change subject: mb/google/brya: Drop primus4es board ...................................................................... mb/google/brya: Drop primus4es board Primus4es board is no longer supported thus drop it from the tree. Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Signed-off-by: Jakub Czapiga <czapiga(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name D src/mainboard/google/brya/variants/primus4es/Makefile.inc D src/mainboard/google/brya/variants/primus4es/fw_config.c D src/mainboard/google/brya/variants/primus4es/gpio.c D src/mainboard/google/brya/variants/primus4es/include/variant/ec.h D src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h D src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc D src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt D src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt D src/mainboard/google/brya/variants/primus4es/overridetree.cb D src/mainboard/google/brya/variants/primus4es/variant.c 13 files changed, 0 insertions(+), 827 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/79916/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index ce0f2e0..18a6575 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -132,7 +132,6 @@ def_bool n config USE_PM_ACPI_TIMER - default y if BOARD_GOOGLE_PRIMUS4ES default n config MEMORY_SODIMM diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index be4e694..e2357f4 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -332,13 +332,6 @@ select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_PRIMUS4ES - select BOARD_GOOGLE_BASEBOARD_BRYA - select DEFAULT_ADL_NEM - select DRIVERS_GENESYSLOGIC_GL9755 - select HAVE_PCIE_WWAN - select HAVE_WWAN_POWER_SEQUENCE - config BOARD_GOOGLE_PUJJO select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -539,7 +532,6 @@ default 0x1 if BOARD_GOOGLE_BRYA0 default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS - default 0x3 if BOARD_GOOGLE_PRIMUS4ES default 0x1 if BOARD_GOOGLE_GIMBLE default 0x3 if BOARD_GOOGLE_GIMBLE4ES default 0x1 if BOARD_GOOGLE_REDRIX @@ -621,7 +613,6 @@ default "Brya" if BOARD_GOOGLE_BRYA0 default "Brask" if BOARD_GOOGLE_BRASK default "Primus" if BOARD_GOOGLE_PRIMUS - default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES default "Gimble" if BOARD_GOOGLE_GIMBLE default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES default "Redrix" if BOARD_GOOGLE_REDRIX @@ -675,7 +666,6 @@ default "brya0" if BOARD_GOOGLE_BRYA0 default "brask" if BOARD_GOOGLE_BRASK default "primus" if BOARD_GOOGLE_PRIMUS - default "primus4es" if BOARD_GOOGLE_PRIMUS4ES default "gimble" if BOARD_GOOGLE_GIMBLE default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES default "redrix" if BOARD_GOOGLE_REDRIX @@ -749,7 +739,6 @@ def_bool n config USE_PM_ACPI_TIMER - default y if BOARD_GOOGLE_PRIMUS4ES default n config DEFAULT_ADL_NEM diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index bb6a4d2..efbdd1a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -96,9 +96,6 @@ config BOARD_GOOGLE_PRIMUS bool "-> Primus" -config BOARD_GOOGLE_PRIMUS4ES - bool "-> Primus4ES" - config BOARD_GOOGLE_PUJJO bool "-> Pujjo" diff --git a/src/mainboard/google/brya/variants/primus4es/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/Makefile.inc deleted file mode 100644 index 725b883..0000000 --- a/src/mainboard/google/brya/variants/primus4es/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-y += gpio.c -ramstage-$(CONFIG_FW_CONFIG) += fw_config.c -ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/primus4es/fw_config.c b/src/mainboard/google/brya/variants/primus4es/fw_config.c deleted file mode 100644 index c9b4a38..0000000 --- a/src/mainboard/google/brya/variants/primus4es/fw_config.c +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootstate.h> -#include <console/console.h> -#include <fw_config.h> -#include <gpio.h> - -static const struct pad_config dmic_enable_pads[] = { - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ -}; - -static const struct pad_config dmic_disable_pads[] = { - PAD_NC(GPP_R4, NONE), - PAD_NC(GPP_R5, NONE), - PAD_NC(GPP_R6, NONE), - PAD_NC(GPP_R7, NONE), -}; - -static const struct pad_config i2s_enable_pads[] = { - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ - PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */ -}; - -static const struct pad_config i2s_disable_pads[] = { - PAD_NC(GPP_R0, NONE), - PAD_NC(GPP_R1, NONE), - PAD_NC(GPP_R2, NONE), - PAD_NC(GPP_R3, NONE), - PAD_NC(GPP_S0, NONE), - PAD_NC(GPP_S1, NONE), - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), -}; - -static const struct pad_config bt_i2s_enable_pads[] = { - PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */ - PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */ - PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */ - PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */ - PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */ - PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */ - PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */ - PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */ -}; - -static const struct pad_config bt_i2s_disable_pads[] = { - PAD_NC(GPP_VGPIO_30, NONE), - PAD_NC(GPP_VGPIO_31, NONE), - PAD_NC(GPP_VGPIO_32, NONE), - PAD_NC(GPP_VGPIO_33, NONE), - PAD_NC(GPP_VGPIO_34, NONE), - PAD_NC(GPP_VGPIO_35, NONE), - PAD_NC(GPP_VGPIO_36, NONE), - PAD_NC(GPP_VGPIO_37, NONE), -}; - - -static void fw_config_handle(void *unused) -{ - if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { - printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); - gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); - gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); - gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads)); - return; - } - - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { - printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); - gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); - gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); - } - - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) { - printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I-VS.\n"); - gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); - gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); - gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads)); - } -} -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c deleted file mode 100644 index 5b04d1f..0000000 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <commonlib/helpers.h> -#include <soc/gpio.h> - -/* Pad configuration in ramstage */ -static const struct pad_config override_gpio_table[] = { - /* A6 : ESPI_ALERT1# ==> NC */ - PAD_NC(GPP_A6, NONE), - /* A7 : SRCCLK_OE7# ==> NC */ - PAD_NC(GPP_A7, NONE), - /* A14 : USB_OC1# ==> NC */ - PAD_NC(GPP_A14, NONE), - /* A15 : USB_OC2# ==> NC */ - PAD_NC(GPP_A15, NONE), - /* A21 : DDPC_CTRCLK ==> NC */ - PAD_NC(GPP_A21, NONE), - /* A22 : DDPC_CTRLDATA ==> NC */ - PAD_NC(GPP_A22, NONE), - - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), - /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), - /* B15 : TIME_SYNC0 ==> NC */ - PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), - - /* C3 : SML0CLK ==> NC */ - PAD_NC(GPP_C3, NONE), - /* C4 : SML0DATA ==> NC */ - PAD_NC(GPP_C4, NONE), - - /* D3 : ISH_GP3 ==> NC */ - PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), - /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* D6 : SRCCLKREQ1# ==> NC */ - PAD_NC(GPP_D6, NONE), - /* D13 : ISH_UART0_RXD ==> NC */ - PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), - /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ - PAD_CFG_GPO_LOCK(GPP_D14, 1, LOCK_CONFIG), - /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), - - /* E3 : PROC_GP0 ==> NC */ - PAD_NC(GPP_E3, NONE), - /* E7 : PROC_GP1 ==> NC */ - PAD_NC(GPP_E7, NONE), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ - PAD_CFG_GPO(GPP_E20, 1, DEEP), - /* E21 : DDP2_CTRLDATA ==> NC */ - PAD_NC(GPP_E21, NONE), - - /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EXT_PWR_GATE# ==> NC */ - PAD_NC(GPP_F20, NONE), - - /* H19 : SRCCLKREQ4# ==> NC */ - PAD_NC(GPP_H19, NONE), - /* H21 : IMGCLKOUT2 ==> NC */ - PAD_NC(GPP_H21, NONE), - /* H22 : IMGCLKOUT3 ==> NC */ - PAD_NC(GPP_H22, NONE), - /* H23 : SRCCLKREQ5# ==> NC */ - PAD_NC(GPP_H23, NONE), - - /* S6 : SNDW3_CLK ==> NC */ - PAD_NC(GPP_S6, NONE), - /* S7 : SNDW3_DATA ==> NC */ - PAD_NC(GPP_S7, NONE), - - /* T2 : GPP_T2 ==> eMMC_CFG */ - PAD_CFG_GPI(GPP_T2, NONE, DEEP), - - /* GPD11: LANPHYC ==> NC */ - PAD_NC(GPD11, NONE), -}; - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), - /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 0, DEEP), - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), - /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), - /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), - /* - * D1 : ISH_GP1 ==> FP_RST_ODL - * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. - * To ensure proper power sequencing for the FPMCU device, reset signal is driven low - * early on in bootblock, followed by enabling of power. Reset signal is deasserted - * later on in ramstage. Since reset signal is asserted in bootblock, it results in - * FPMCU not working after a S3 resume. This is a known issue. - */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), - /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), - /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 0, PLTRST), - /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage)*/ - PAD_CFG_GPO(GPP_E0, 0, DEEP), - /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), - /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage)*/ - PAD_CFG_GPO(GPP_E16, 0, DEEP), - /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), - /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ - PAD_CFG_GPO(GPP_E20, 1, DEEP), - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), - /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), - /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), - /* H13 : I2C7_SCL ==> EN_PP3300_SD */ - PAD_CFG_GPO(GPP_H13, 1, PLTRST), -}; - -static const struct pad_config romstage_gpio_table[] = { - /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */ - PAD_CFG_GPO(GPP_A12, 1, DEEP), - - /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), - - /* Enable touchscreen, hold in reset */ - /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ - PAD_CFG_GPO(GPP_C0, 1, DEEP), - /* C1 : SMBDATA ==> USI_RST_L */ - PAD_CFG_GPO(GPP_C1, 0, DEEP), - - /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 0, DEEP), - - /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */ - PAD_CFG_GPO(GPP_F21, 1, DEEP), -}; - -const struct pad_config *variant_gpio_override_table(size_t *num) -{ - *num = ARRAY_SIZE(override_gpio_table); - return override_gpio_table; -} - -const struct pad_config *variant_early_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; -} - -const struct pad_config *variant_romstage_gpio_table(size_t *num) -{ - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; -} diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h b/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h deleted file mode 100644 index 7309098..0000000 --- a/src/mainboard/google/brya/variants/primus4es/include/variant/ec.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __VARIANT_EC_H__ -#define __VARIANT_EC_H__ - -#include <baseboard/ec.h> - -/* Enable PS/2 Mouse */ -#define SIO_EC_ENABLE_PS2M - -#endif diff --git a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h deleted file mode 100644 index cbf6040..0000000 --- a/src/mainboard/google/brya/variants/primus4es/include/variant/gpio.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <baseboard/gpio.h> -#define WWAN_FCPO GPP_F21 -#define WWAN_RST GPP_E16 -#define WWAN_PERST GPP_E0 -#define T1_OFF_MS 16 -#define T2_OFF_MS 2 - -#endif diff --git a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc deleted file mode 100644 index d2fae29..0000000 --- a/src/mainboard/google/brya/variants/primus4es/memory/Makefile.inc +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt - -SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D1NP-046 WT:B -SPD_SOURCES += spd/lp4x/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9HCNNNFAMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, MT53E1G32D2NP-046 WT:B, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt deleted file mode 100644 index cdaaac0..0000000 --- a/src/mainboard/google/brya/variants/primus4es/memory/dram_id.generated.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/primus/memory src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt - -DRAM Part Name ID to assign -H9HCNNNBKMMLXR-NEE 0 (0000) -H9HCNNNFAMMLXR-NEE 1 (0001) -H9HCNNNCPMMLXR-NEE 2 (0010) -K4U6E3S4AA-MGCR 0 (0000) -MT53E512M32D1NP-046 WT:B 0 (0000) -MT53E1G32D2NP-046 WT:B 2 (0010) -K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt deleted file mode 100644 index bb14464..0000000 --- a/src/mainboard/google/brya/variants/primus4es/memory/mem_parts_used.txt +++ /dev/null @@ -1,7 +0,0 @@ -H9HCNNNBKMMLXR-NEE -H9HCNNNFAMMLXR-NEE -H9HCNNNCPMMLXR-NEE -K4U6E3S4AA-MGCR -MT53E512M32D1NP-046 WT:B -MT53E1G32D2NP-046 WT:B -K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb deleted file mode 100644 index baec228..0000000 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ /dev/null @@ -1,428 +0,0 @@ -fw_config - field DB_USB 0 3 - option USB_ABSENT 0 - option USB3_PS8811 1 - end - field DB_SD 4 5 - option SD_ABSENT 0 - option SD_GL9755S 1 - end - field KB_BL 7 7 - option KB_BL_ABSENT 0 - option KB_BL_PRESENT 1 - end - field AUDIO 8 10 - option AUDIO_UNKNOWN 0 - option MAX98360_ALC5682I_I2S 1 - option MAX98360_ALC5682I_VS_I2S 2 - end - field DB_LTE 11 12 - option LTE_ABSENT 0 - option LTE_USB 1 - end -end - -chip soc/intel/alderlake - register "sagv" = "SaGv_Enabled" - register "max_dram_speed_mts" = "3733" - - # Acoustic settings - register "acoustic_noise_mitigation" = "1" - register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" - register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" - register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" - register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI1 | Fingerprint MCU | - #| I2C0 | Audio | - #| I2C1 | Touchscreen | - #| I2C2 | | - #| I2C3 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| I2C5 | Trackpad | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - - register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port - register "usb3_ports[2]" = "USB3_PORT_EMPTY" - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" - - device domain 0 on - device ref igpu on - chip drivers/gfx/generic - register "device_count" = "6" - # DDIA for eDP - register "device[0].name" = ""LCD"" - # DDIB for HDMI - register "device[1].name" = ""DD01"" - # TCP0 (DP-1) for port C0 - register "device[2].name" = ""DD02"" - register "device[2].use_pld" = "true" - register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" - # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 - register "device[3].name" = ""DD03"" - # TCP2 (DP-3) for port C2 - register "device[4].name" = ""DD04"" - register "device[4].use_pld" = "true" - register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 - register "device[5].name" = ""DD05"" - device generic 0 on end - end - end # Integrated Graphics Device - device ref dtt on - chip drivers/intel/dptf - ## sensor information - register "options.tsr[0].desc" = ""CPU"" - register "options.tsr[1].desc" = ""SSD"" - register "options.tsr[2].desc" = ""CHARGER"" - register "options.tsr[3].desc" = ""MEMORY"" - register "options.tsr[4].desc" = ""TYPEC"" - # TODO: below values are initial reference values only - - ## Passive Policy - register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), - [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), - [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), - - }" - - ## Critical Policy - register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), - [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), - }" - - register "controls.power_limits" = "{ - .pl1 = { - .min_power = 3000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 250, - }, - .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000, - } - }" - - ## Charger Performance Control (Control, mA) - register "controls.charger_perf" = "{ - [0] = { 255, 1700 }, - [1] = { 24, 1500 }, - [2] = { 16, 1000 }, - [3] = { 8, 500 } - }" - device generic 0 alias dptf_policy on end - end - end - device ref cnvi_wifi on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end - device ref pcie_rp3 on - chip soc/intel/common/block/pcie/rtd3 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" - register "srcclk_pin" = "6" - register "reset_delay_ms" = "50" - register "enable_delay_ms" = "20" - device generic 0 alias emmc_rtd3 on end - end - # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 - register "pch_pcie_rp[PCH_RP(3)]" = "{ - .clk_src = 6, - .clk_req = 6, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE3 BH799BB - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end - device ref tcss_dma1 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port3 as dfp[0].typec_port - device generic 0 on end - end - end - device ref pcie_rp6 off end #PCIE6 WWAN - device ref pcie_rp8 on - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" - register "srcclk_pin" = "3" - device generic 0 on end - end - end #PCIE8 SD card - device ref pcie_rp9 on - # Enable NVMe PCIE 9 using clk 0 - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 0, - .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE9-12 SSD - device ref i2c0 on - chip drivers/i2c/generic - register "hid" = ""10EC5682"" - register "name" = ""RT58"" - register "desc" = ""Headset Codec"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" - # Set the jd_src to RT5668_JD1 for jack detection - register "property_count" = "1" - register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" - register "property_list[0].name" = ""realtek,jd-src"" - register "property_list[0].integer" = "1" - device i2c 1a alias audio_codec on - probe AUDIO MAX98360_ALC5682I_I2S - probe AUDIO MAX98360_ALC5682I_VS_I2S - end - end - end #I2C0 - device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN9050"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "200" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" - register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "50" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x40 on end - end - end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end - device ref i2c5 on - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" - register "wake" = "GPE0_DW2_14" - register "detect" = "1" - device i2c 15 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GXTP7288"" - register "generic.desc" = ""Goodix Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "generic.wake" = "GPE0_DW2_14" - register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 2c on end - end - end - device ref hda on - chip drivers/generic/max98357a - register "hid" = ""MX98360A"" - register "sdmode_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" - register "sdmode_delay" = "5" - device generic 0 on - probe AUDIO MAX98360_ALC5682I_I2S - probe AUDIO MAX98360_ALC5682I_VS_I2S - end - end - end - device ref gspi1 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" - register "has_power_resource" = "1" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" - register "enable_delay_ms" = "3" - device spi 0 hidden end - end # FPMCU - end - device ref pch_espi on - chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] - device pnp 0c09.0 on end - end - end - device ref pmc hidden - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end - end - chip drivers/intel/pmc_mux/conn - use usb2_port3 as usb2_port - use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end - end - end - end - end - device ref tcss_xhci on - chip drivers/usb/acpi - device ref tcss_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C2 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port3 on end - end - end - end - end - device ref xhci on - chip drivers/usb/acpi - device ref xhci_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" - device ref usb2_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C2 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_A" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb2_port8 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (DB)"" - register "type" = "UPC_TYPE_A" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - device ref usb2_port9 on end - end - chip drivers/usb/acpi - register "desc" = ""USB2 Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port10 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (DB)"" - register "type" = "UPC_TYPE_USB3_A" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" - device ref usb3_port1 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port (MLB)"" - register "type" = "UPC_TYPE_USB3_A" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" - device ref usb3_port2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device ref usb3_port4 on end - end - end - end - end - end -end diff --git a/src/mainboard/google/brya/variants/primus4es/variant.c b/src/mainboard/google/brya/variants/primus4es/variant.c deleted file mode 100644 index e78dfdc..0000000 --- a/src/mainboard/google/brya/variants/primus4es/variant.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <boardid.h> -#include <device/device.h> -#include <drivers/i2c/hid/chip.h> -#include <fw_config.h> -#include <gpio.h> - -static void devtree_update_emmc_rtd3(uint32_t board_ver) -{ - struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3); - if (board_ver > 1) - return; - - emmc_rtd3->enabled = 0; -} - -static void devtree_update_audio_codec(void) -{ - struct device *audio_codec = DEV_PTR(audio_codec); - struct drivers_i2c_generic_config *config = audio_codec->chip_info; - - if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_VS_I2S))) - config->hid = "RTL5682"; -} - -static const struct pad_config nvme_disable_pads[] = { - PAD_NC(GPP_B2, NONE), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ - PAD_NC(GPP_B4, NONE), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_NC(GPP_D3, NONE), /* D3 : ISH_GP3 ==> M2_SSD_PLN_L */ - PAD_NC(GPP_D5, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ - PAD_NC(GPP_D11, NONE), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ -}; - -static const struct pad_config emmc_disable_pads[] = { - PAD_NC(GPP_B3, NONE), /* B3 : PROC_GP2 ==> eMMC_PERST_L */ - PAD_NC(GPP_E20, NONE), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ - PAD_NC(GPP_F19, NONE), /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ -}; - -static void disable_unused_gpios(void) -{ - int emmc_detected = gpio_get(GPP_T2); - - if (emmc_detected == 1) - gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); - else - gpio_configure_pads(emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); -} - -void variant_devtree_update(void) -{ - uint32_t board_ver = board_id(); - disable_unused_gpios(); - devtree_update_emmc_rtd3(board_ver); - devtree_update_audio_codec(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/79916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0502b2eed6f80d648b422c8d1622d504a6c93822 Gerrit-Change-Number: 79916 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <czapiga(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: [UNTESTED] soc/amd/genoa_poc: add CPPC support
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Marshall Dawson, Martin L Roth, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79528?usp=email ) Change subject: [UNTESTED] soc/amd/genoa_poc: add CPPC support ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: hmm, the cppc package matches between the uefi reference firmware and coreboot+opensil with this patch applied except for the last two values. expected is 0x00000190, 0x00000867, but we get 0x00000867, 0x00000000 which smells like an off by one in the smu mailbox command IDs to me -- To view, visit https://review.coreboot.org/c/coreboot/+/79528?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc40a92810e845dc8eeba3908f5bfce274df2ab9 Gerrit-Change-Number: 79528 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Jan 2024 15:18:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79858?usp=email ) Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar ...................................................................... mb/google/nissa/var/anraggar: add FW config to apply the wifi sar 1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs to load a SAR table. 2.Describe the FW_CONFIG probe for the settings. - WIFI_6 for MTK Wi-Fi module MT7921L - WIFI_6E for Intel Wi-Fi module AX211NGW BUG=b:315418153 TEST=emerge-nissa coreboot Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/anraggar/variant.c 2 files changed, 7 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 8fe4316..2c4cecc 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -1,4 +1,9 @@ fw_config + field WIFI 10 11 + option UNKNOWN 0 + option WIFI_6 1 + option WIFI_6E 2 + end field CAMERA 12 13 option UF_720P_WF 0 option UF_1080P 1 diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c index 4f44c38..4221a5b 100644 --- a/src/mainboard/google/brya/variants/anraggar/variant.c +++ b/src/mainboard/google/brya/variants/anraggar/variant.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <fw_config.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) { - return "wifi_sar_2.hex"; + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Gerrit-Change-Number: 79858 Gerrit-PatchSet: 6 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: lib/fw_config: Remove redundant stdbool and stdint
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79911?usp=email ) Change subject: lib/fw_config: Remove redundant stdbool and stdint ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie8676769127d21a3b4693ed947a7231b94e99241 Gerrit-Change-Number: 79911 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 12 Jan 2024 14:54:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: tree: Remove duplicated includes
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79912?usp=email ) Change subject: tree: Remove duplicated includes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79912?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09dd5871cb366ef95410efc1ca6c4337f23b52fd Gerrit-Change-Number: 79912 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 12 Jan 2024 14:54:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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