coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

[L] Change in coreboot[main]: intel skl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michał Żygowski, Nico Huber, Piotr Król. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79958?usp=email ) Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 3: (2 comments) File src/mainboard/purism/librem_skl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79958/comment/b33dba34_cc2a22c0 : PS2, Line 156: device ref pcie_rp1 on end > @Felix could you remove pcie_rp1 please? There's nothing on this port, it was evidently here to ena […] Yeah, it's probably enabled in order to enable the others. Please make a separate patch for that. It's hard to reason removals when the commit message is about moving things. File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79958/comment/3c425ef0_13ff1af9 : PS2, Line 185: device ref pcie_rp1 on end > I mentioned this on CL79917 too, I think pcie_rp1 was enabling the promoted pcie_rp3, it's similar t […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/79958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Gerrit-Change-Number: 79958 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:09:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Felix Singer, Martin L Roth, Marvin Evers, Matt DeVillier. Felix Singer has uploaded a new patch set (#10) to the change originally created by Marvin Evers. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... mb/google/poppy: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 7 files changed, 380 insertions(+), 380 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79439/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 10 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel: Add Lunar Lake device IDs
by Wonkyu Kim (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Appukuttan V K, Ashish Kumar Mishra, Bora Guvendik, Saurabh Mishra. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79899?usp=email ) Change subject: soc/intel: Add Lunar Lake device IDs ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0aae6fd7aa8ba3a6a794f8af5ecf3967509b704 Gerrit-Change-Number: 79899 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 19:47:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common: Add lunarlake device IDs
by Wonkyu Kim (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Appukuttan V K, Ashish Kumar Mishra, Bora Guvendik, Saurabh Mishra. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79900?usp=email ) Change subject: soc/intel/common: Add lunarlake device IDs ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31d567287b9921d60909b1eb617c7cfaf6672c9 Gerrit-Change-Number: 79900 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 19:47:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Felix Singer, Martin L Roth, Marvin Evers, Matt DeVillier. Felix Singer has uploaded a new patch set (#9) to the change originally created by Marvin Evers. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... mb/google/poppy: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 7 files changed, 380 insertions(+), 380 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79439/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 9 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integer
by Mike Banon (Code Review) 17 Jan '24

17 Jan '24

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79842?usp=email ) Change subject: soc/intel/mtl: Override the `SOC_PHYSICAL_ADDRESS_WIDTH` as integer ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Thank you very much for fixing this, now I can remove the git revert of CB:79666 from restore_agesa.sh at CB:79838 -- To view, visit https://review.coreboot.org/c/coreboot/+/79842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5bdfdb8c2689803c9d3c2bfd353609edae91ab3 Gerrit-Change-Number: 79842 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 19:11:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: intel skl mainboards: Move PcieRpEnable option below dt entries
by Jonathon Hall (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Erik van den Bogaert, Felix Singer, Frans Hendriks, Michał Żygowski, Nico Huber, Piotr Król. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79958?usp=email ) Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 3: (2 comments) File src/mainboard/purism/librem_skl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79958/comment/4cf81872_3a113dd9 : PS2, Line 156: device ref pcie_rp1 on end @Felix could you remove pcie_rp1 please? There's nothing on this port, it was evidently here to enable the promoted pcie_rp5 function. I just tested it with pcie_rp5 and pcie_rp9 and confirmed both WLAN and NVMe work. Or if you would prefer a separate CL for this from me, let me know. Also mentioned this on CL79917. File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79958/comment/b0002761_e4b08f7a : PS2, Line 185: device ref pcie_rp1 on end I mentioned this on CL79917 too, I think pcie_rp1 was enabling the promoted pcie_rp3, it's similar to librem_skl. pcie_rp1 is probably not needed with pcie_rp3 having been added. I don't have this board though and MAINTAINERS says it's orphaned -- To view, visit https://review.coreboot.org/c/coreboot/+/79958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda Gerrit-Change-Number: 79958 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 18:40:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable
by Jonathon Hall (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Angel Pons, Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email ) Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ...................................................................... Patch Set 2: (2 comments) File src/mainboard/purism/librem_skl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79917/comment/b77046a0_789c54fd : PS2, Line 141: register "PcieRpEnable[4]" = "1" > I don't know why librem_skl has pcie_rp1 in the device tree, but enables PcieRpEnable[4] here. […] Tested librem_13v2. The device tree should have pcie_rp5, not pcie_rp1. It did work before, but breaks in this CL, WLAN no longer works. Changing that fixes it. It looks to me like pcie_rp1 was there to enable the promoted pcie_rp5 PCI function (it was a literal PCI dev/fn before some other refactoring). @Nico could you change that please, or let me know if you would like a separate CL? This also overlaps with CL79958, I'll mention this there too. File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79917/comment/7f62ad55_b87df47f : PS2, Line 190: device ref pcie_rp1 on end I don't have this board, but based on what I found on librem_skl, I bet this is supposed to be pcie_rp3. (Noticed this also when comparing librem_skl to other boards in this CL.) MAINTAINERS lists all razer boards as orphaned though -- To view, visit https://review.coreboot.org/c/coreboot/+/79917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Gerrit-Change-Number: 79917 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 18:35:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel: Unify the definition of TCO registers
by Marek Maślanka (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jeff Daly, Johnny Lin, Marek Maślanka, Sean Rhodes, Tim Chu, Vanessa Eusebio. Hello Arthur Heymans, Christian Walter, Jeff Daly, Johnny Lin, Sean Rhodes, Tim Chu, Vanessa Eusebio, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80005?usp=email to look at the new patch set (#8). Change subject: soc/intel: Unify the definition of TCO registers ...................................................................... soc/intel: Unify the definition of TCO registers Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Only leaves those TCO register definitions that are incompatible. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka(a)google.com> --- M src/soc/intel/apollolake/elog.c M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/pch/include/intelpch/smbus.h A src/soc/intel/common/tco.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/xeon_sp/include/soc/smbus.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c 11 files changed, 64 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80005/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Gerrit-Change-Number: 80005 Gerrit-PatchSet: 8 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd/phoenix/Kconfig: factor out FSP-specific options
by Felix Held (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79983?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix/Kconfig: factor out FSP-specific options ...................................................................... soc/amd/phoenix/Kconfig: factor out FSP-specific options Split the SOC_AMD_PHOENIX Kconfig option into SOC_AMD_PHOENIX_BASE that selects the non-FSP-specific options and SOC_AMD_PHOENIX_FSP that selects both SOC_AMD_PHOENIX_BASE and the FSP-specific options. This will help to separate the FSP-specific from the FSP-agnostic code. The mainboards using this SoC now select SOC_AMD_PHOENIX_FSP instead of SOC_AMD_PHOENIX. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/mayan/Kconfig M src/mainboard/google/myst/Kconfig M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 5 files changed, 24 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79983/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79983?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e95fbfd9d16930ba3e6cc497557d61adba5a6fa Gerrit-Change-Number: 79983 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024