coreboot-gerrit January 2024

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Matt DeVillier (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Felix Singer, Martin L Roth, Marvin Evers. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 11 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:36:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Maximilian Brune, Paul Menzel, Zebreus. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78884?usp=email ) Change subject: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6 ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78884/comment/5ac0dc8c_c916b4f7 : PS1, Line 8: > Not currently, but you could help by doing that testing and adding the statistics. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Gerrit-Change-Number: 78884 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Paul Menzel, Zebreus. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78884?usp=email ) Change subject: util/crossgcc: Update LLVM from 16.0.6 to 17.0.6 ...................................................................... Patch Set 8: (2 comments) Patchset: PS1: > Maximilian, Arthur, could you have a look on these issues? […] Done PS1: > ``` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6 Gerrit-Change-Number: 78884 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:28:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/poppy: Use chipset dt reference names
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Felix Singer, Martin L Roth, Marvin Evers, Matt DeVillier. Felix Singer has uploaded a new patch set (#11) to the change originally created by Marvin Evers. ( https://review.coreboot.org/c/coreboot/+/79439?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/poppy: Use chipset dt reference names ...................................................................... mb/google/poppy: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 7 files changed, 380 insertions(+), 380 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79439/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/79439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d Gerrit-Change-Number: 79439 Gerrit-PatchSet: 11 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: arch/x86/mpspec: turn compile-time check into Kconfig dependency
by Felix Held (Code Review) 17 Jan '24

17 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79994?usp=email ) Change subject: arch/x86/mpspec: turn compile-time check into Kconfig dependency ...................................................................... arch/x86/mpspec: turn compile-time check into Kconfig dependency Instead of checking if there is more than one PCI segment group and erroring out in that case during the build, add this requirement as a dependency to the GENERATE_MP_TABLE Kconfig option. The mpspec.c source file only gets included in the build if GENERATE_MP_TABLE is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79994 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/Kconfig M src/arch/x86/mpspec.c 2 files changed, 1 insertion(+), 4 deletions(-) Approvals: Martin Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/Kconfig b/src/Kconfig index 7867f44..21c50c5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -906,6 +906,7 @@ config GENERATE_MP_TABLE prompt "Generate an MP table" if HAVE_MP_TABLE bool + depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 default HAVE_MP_TABLE help Generate an MP table (conforming to the Intel MultiProcessor diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 3b4c8ad..7744f68 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -14,10 +14,6 @@ #include <stdint.h> #include <string.h> -#if CONFIG(ECAM_MMCONF_SUPPORT) && PCI_SEGMENT_GROUP_COUNT > 1 -#error "MPTable doesn't support systems with multiple PCI segment groups" -#endif - /* Initialize the specified "mc" struct with initial values. */ void mptable_init(struct mp_config_table *mc) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 Gerrit-Change-Number: 79994 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: intel ehl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79961?usp=email ) Change subject: intel ehl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Abandoned superseded by CB:79921 -- To view, visit https://review.coreboot.org/c/coreboot/+/79961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b14704916bb8105837257c271576f30cf62138b Gerrit-Change-Number: 79961 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: intel ehl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79961?usp=email ) Change subject: intel ehl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Not sure if we need this patch at all as CB:79921 already just removes the entries in question. […] Right, the amount of mainboards is small enough for reviewing there. -- To view, visit https://review.coreboot.org/c/coreboot/+/79961?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b14704916bb8105837257c271576f30cf62138b Gerrit-Change-Number: 79961 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel: Unify the definition of TCO registers
by Marek Maślanka (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jakub Czapiga, Jeff Daly, Johnny Lin, Sean Rhodes, Tim Chu, Vanessa Eusebio. Marek Maślanka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80005?usp=email ) Change subject: soc/intel: Unify the definition of TCO registers ...................................................................... Patch Set 8: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80005/comment/e5637b32_11cb49bb : PS6, Line 9: Move TCO registers definition to a separate file and use it : consistently. > Please add, why some TCO definitions still stay in different files sometimes. Added some explanation. Let me know if it's enough, File src/soc/intel/common/tco.h: https://review.coreboot.org/c/coreboot/+/80005/comment/d483ec61_6e8e43b6 : PS6, Line 11: TCO_STS_TCO_SLVSEL > Some symbols have TCO numbers and some do not. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Gerrit-Change-Number: 80005 Gerrit-PatchSet: 8 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:14:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <czapiga(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: intel tgl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79960?usp=email ) Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/volteer/variants/voema/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79960/comment/a4d5c8fc_69f50bc0 : PS1, Line 108: probe DB_SD SD_GL9755S : probe DB_SD SD_RTS5261 : probe DB_SD SD_RTS5227S : probe DB_SD SD_GL9750 : probe DB_SD SD_OZ711LV2LN > Removed the entries but it broke the build. […] Nico confirmed my assumption. The probe entries are necessary, else it's a new device. I've added them again. -- To view, visit https://review.coreboot.org/c/coreboot/+/79960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e Gerrit-Change-Number: 79960 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 17 Jan 2024 20:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: intel tgl mainboards: Move PcieRpEnable option below dt entries
by Felix Singer (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Matt DeVillier, Nick Vaccaro. Hello Matt DeVillier, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79960?usp=email to look at the new patch set (#3). Change subject: intel tgl mainboards: Move PcieRpEnable option below dt entries ...................................................................... intel tgl mainboards: Move PcieRpEnable option below dt entries There is work being done on better integrating the root port entries from the devicetree by hooking up the FSP option PcieRpEnable to them, which supersedes the devicetree option. Move the PcieRpEnable option below their related devicetree entries in order to make the review easier when the option is removed. Create devicetree entries in case of they don't exist yet. Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 6 files changed, 51 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79960/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65bf27342191129b433d779774e084eecb4e4b3e Gerrit-Change-Number: 79960 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024