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Change subject: mb/arm/rdn2: Add support for Arm Neoverse N2
......................................................................
mb/arm/rdn2: Add support for Arm Neoverse N2
Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com>
---
A src/mainboard/arm/Kconfig
A src/mainboard/arm/Kconfig.name
A src/mainboard/arm/rdn2/Kconfig
A src/mainboard/arm/rdn2/Kconfig.name
A src/mainboard/arm/rdn2/Makefile.inc
A src/mainboard/arm/rdn2/acpi.c
A src/mainboard/arm/rdn2/board_info.txt
A src/mainboard/arm/rdn2/bootblock.c
A src/mainboard/arm/rdn2/bootblock_custom.S
A src/mainboard/arm/rdn2/cbmem.c
A src/mainboard/arm/rdn2/chip.h
A src/mainboard/arm/rdn2/devicetree.cb
A src/mainboard/arm/rdn2/dsdt.asl
A src/mainboard/arm/rdn2/flash.fmd
A src/mainboard/arm/rdn2/include/mainboard/addressmap.h
A src/mainboard/arm/rdn2/mainboard.c
A src/mainboard/arm/rdn2/media.c
A src/mainboard/arm/rdn2/memlayout.ld
A src/mainboard/arm/rdn2/mmio.c
A src/mainboard/arm/rdn2/pptt.c
20 files changed, 1,138 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/79103/6
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Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
......................................................................
Patch Set 15: Code-Review+1
(1 comment)
Patchset:
PS15:
indent update
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Shuo Liu has uploaded a new patch set (#15) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/78333?usp=email )
The following approvals got outdated and were removed:
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Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
......................................................................
soc/intel/xeon_sp: Add IIO resources via SSDT
There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8
---
M src/soc/intel/xeon_sp/acpi/iiostack.asl
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
11 files changed, 47 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78333/15
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Change subject: mb/arm/rdn2: Add support for Arm Neoverse N2
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/arm/rdn2/acpi.c:
https://review.coreboot.org/c/coreboot/+/79103/comment/0a020222_e080903c :
PS5, Line 29: platform_get_gicd_base
> Why does it use GICv2 compatibility mode?
Yes. Will remove
https://review.coreboot.org/c/coreboot/+/79103/comment/36adb702_4d2e40e0 :
PS5, Line 30: gicv
> only needed on GICv2
Acknowledged
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Change subject: [RFC] region: Turn region_end() into an inclusive region_last()
......................................................................
Patch Set 6:
(3 comments)
File src/commonlib/region.c:
https://review.coreboot.org/c/coreboot/+/79946/comment/00f89643_8477c6f5 :
PS5, Line 16: if (region_last(c) < region_offset(p))
> Sorry, about that, I really messed up the push. It's not the final version […]
Restored the original check.
In the current version the check is partially redundant with the one in
normalize_and_ok(), and shouldn't be necessary if we decide to allow only
legal regions.
File src/drivers/spi/winbond.c:
https://review.coreboot.org/c/coreboot/+/79946/comment/c09640dd_9523d5d7 :
PS5, Line 505: region_last(region) + 1
> Yes, it would be better to use `flash->size - 1`. I guess we shouldn't […]
Done
File tests/commonlib/region-test.c:
https://review.coreboot.org/c/coreboot/+/79946/comment/f4ac3605_0d8133ff :
PS5, Line 338: assert_true((uintptr_t)backing <= SIZE_MAX);
> This was about asserting the unit-test was valid. I probably have seen too many […]
Done
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I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: [RFC] region: Turn region_end() into an inclusive region_last()
......................................................................
[RFC] region: Turn region_end() into an inclusive region_last()
The current region_end() implementation is susceptible to overflow
if the region is at the end of the addressable space. A common case
with the memory-mapped flash of x86 directly below the 32-bit limit.
Note: The current patch also changes console output to inclusive
limits. IMO, to the better.
Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/commonlib/include/commonlib/region.h
M src/commonlib/region.c
M src/cpu/x86/smm/smm_module_loader.c
M src/drivers/spi/winbond.c
M tests/commonlib/region-test.c
M tests/lib/region_file-test.c
M util/cbfstool/cbfstool.c
M util/cbfstool/cse_serger.c
8 files changed, 24 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79946/6
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Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Missing google/poppy. Waiting for CB:79439 to get finished.
Done
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Change subject: mb/google/poppy: Use chipset dt reference names
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
I can't submit the patch since I modified it.
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Change subject: mb/google/poppy: Use chipset dt reference names
......................................................................
Patch Set 8: Code-Review+2
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