coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: [RFC] region: Introduce region_create() functions
by Nico Huber (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Andrey Petrov, Julius Werner, Jérémy Compostella, Martin L Roth, Maximilian Brune, Ronak Kanabar. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79905?usp=email ) Change subject: [RFC] region: Introduce region_create() functions ...................................................................... Patch Set 6: (2 comments) File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/c/coreboot/+/79905/comment/b7adbd88_8d799ff0 : PS1, Line 106: offset > SIZE_MAX || size > SIZE_MAX > I agree with Max, I don't really see the point of this (and changing all the types to `unsigned long […] Well, the _unstrusted version is supposed to not make assumptions, but here we are, making assumptions. We can also _Static_assert() some of them, e.g. `SIZE_MAX >= ULONG_MAX`. I guess the current usage is that we deal with input from pointers and strtoul(). And that would be covered. But here is a (for now hypothetical) scenario that wouldn't be: somebody reads a 64-bit BAR and feeds us that. If we add an _untrusted version, we should cover for all eventualities. If we decide for the alternative to always validate inputs manually before calling into the region API (and pray that everybody always gets it right), we don't have to discuss this further. File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/79905/comment/c59a7198_ff7169a4 : PS1, Line 334: if (region_create_untrusted( > They're parsed via `strtol()` so they already cannot overflow a `size_t`. It's good that you know that. But IMHO too much to expect every developer and reviewer to have in mind. The idea of region_create_untrusted() is to provide something that is safe to use, no matter what. And to have a common way to validate unstrusted input. I don't like the alternative we currently live. Which I guess is, assume the developer does the right checks ahead, wait for somebody to perform some verification, file a bug, and only then fix things. -- To view, visit https://review.coreboot.org/c/coreboot/+/79905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae3e6274c981c9ab4fb1263c2a72fa68ef1c32b Gerrit-Change-Number: 79905 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 10:45:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [NEEDS TEST] region: Check for overflows after offset calculation
by Nico Huber (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Julius Werner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79945?usp=email ) Change subject: [NEEDS TEST] region: Check for overflows after offset calculation ...................................................................... Patch Set 3: (2 comments) File src/commonlib/region.c: https://review.coreboot.org/c/coreboot/+/79945/comment/2426522a_4293acaf : PS3, Line 16: if (region_end(c) < region_offset(c)) > I don't think this patch is necessary because this check here basically already checks for exactly t […] It's not 100% the same thing, and IMHO, it looked like it's in the wrong place. This version would wrongfully bail out for a child region that ends exactly at the end of the address space. It's a good thing, though, because now we know we don't have rdev chains in our codebase that would do this (I actually suspected this might be the case on x86). I saw your patch earlier, and thank you for that! I was very puzzled by the code before I saw it. About wrong place or not, IMO, we should decide first if we want to allow only legal regions to be passed between functions. See also https://ticket.coreboot.org/issues/522 From my point of view, we should probably put asserts everywhere (assuming that's not too much overhead). Or at least in all non-static APIs, and act as if they were there in the static functions. https://review.coreboot.org/c/coreboot/+/79945/comment/527567f0_232110d1 : PS3, Line 25: return region_end(inner) - 1 >= region_offset(inner) && This version of the check would allow an inner region at the end of the address space, but not an empty one. I guess that's also something to decide: is an empty region legal? So far the opinions I've heard said no. And I agree. -- To view, visit https://review.coreboot.org/c/coreboot/+/79945?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6054e6e9b6f13502351a2d94c8a0af15266e43e Gerrit-Change-Number: 79945 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 17 Jan 2024 10:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel: Unify the definition of TCO registers
by Jakub Czapiga (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jeff Daly, Johnny Lin, Marek Maślanka, Sean Rhodes, Tim Chu, Vanessa Eusebio. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80005?usp=email ) Change subject: soc/intel: Unify the definition of TCO registers ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80005/comment/8d2b3b75_30e17da2 : PS6, Line 9: Move TCO registers definition to a separate file and use it : consistently. Please add, why some TCO definitions still stay in different files sometimes. File src/soc/intel/common/tco.h: https://review.coreboot.org/c/coreboot/+/80005/comment/e85c005a_6dc2e9bd : PS6, Line 11: TCO_STS_TCO_SLVSEL Some symbols have TCO numbers and some do not. I think they should be unified in that regard, so IMO all symbols should have TCO1_, TCO2_ etc if they describe fields of TCOn. -- To view, visit https://review.coreboot.org/c/coreboot/+/80005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Gerrit-Change-Number: 80005 Gerrit-PatchSet: 6 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 10:24:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Marek Maślanka (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Jakub Czapiga. Marek Maślanka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/apollolake/include/soc/smbus.h: -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 7 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 10:09:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <czapiga(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add IIO resources via SSDT
by Shuo Liu (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78333?usp=email ) Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT ...................................................................... Patch Set 13: Code-Review+1 (2 comments) Patchset: PS13: archercity boot pass with below change list https://review.coreboot.org/c/coreboot/+/78334/12 https://review.coreboot.org/c/coreboot/+/78329 https://review.coreboot.org/c/coreboot/+/78333/12 File src/soc/intel/xeon_sp/spr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/78333/comment/9244f3e8_b37d9cb2 : PS12, Line 382: create_dsdt_iou_cxl_resource(socket, stack, ri, stack_enabled); here we need to check dynamically whether an CXL card is connected to the stack using is_iio_cxl_stack_res(ri) -- To view, visit https://review.coreboot.org/c/coreboot/+/78333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I691d7497dceb89619652e5523a29ea30a7b0fab8 Gerrit-Change-Number: 78333 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 09:52:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Marek Maślanka (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Marek Maślanka. Hello Jakub Czapiga, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79909?usp=email to look at the new patch set (#7). Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... soc/intel/common/block: Add support for watchdog Implement watchdog for intel based platform by filling ACPI Watchdog Action Table (WDAT) table. The WDAT ACPI table encompasses essential watchdog functions, including: - Setting and retrieving countdown/timeout values - Starting and stopping the watchdog - Pinging the watchdog - Retrieving the cause of the last reboot, whether it was triggered by the watchdog or another reason The general purpose register TCO_MESSAGE1 stores the reason for the most recent reboot rather than the original register TCO2_STS. This is because the firmware must clear TCO2_STS, and it can't be reused for storing this information for the operating system. The watchdog is designed for use by the OS through certain defined actions in the WDAT table. It relies on the ACPI Power Management Timer, which may result in an increase in power consumption. BUG=b:314260167 TEST=Enable CONFIG_ACPI_WDAT_WDT and CONFIG_USE_PM_ACPI_TIMER in the config. Enable CONFIG_WDAT_WDT in the kernel config. Build and deploy both firmware and kernel to the device. Trigger the watchdog by performing the command: “cat > /dev/watchdog”. Wait approximately 30 seconds for the watchdog to reset the device. Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Signed-off-by: Marek Maslanka <mmaslanka(a)google.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c 3 files changed, 136 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79909/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 7 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marek Maślanka <mmaslanka(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: Reland "Kconfig: Bring HEAP_SIZE to a common, large value"
by Subrata Banik (Code Review) 17 Jan '24

17 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80023?usp=email ) Change subject: Reland "Kconfig: Bring HEAP_SIZE to a common, large value" ...................................................................... Reland "Kconfig: Bring HEAP_SIZE to a common, large value" This reverts commit acbc4912375085a099c2427def464d6e481f2a90. Reason for revert: CB:79525 fixes the issue that led to the revert by not maintaining the heap in the SMM-stored copy of ramstage at all. Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023 Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig M src/cpu/qemu-x86/Kconfig M src/mainboard/sifive/hifive-unleashed/Kconfig M src/northbridge/amd/pi/Kconfig M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/cavium/cn81xx/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig 21 files changed, 1 insertion(+), 82 deletions(-) Approvals: Julius Werner: Looks good to me, approved Arthur Heymans: Looks good to me, approved Sean Rhodes: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/Kconfig b/src/Kconfig index 5cb9a1a..7867f44 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -759,8 +759,7 @@ config HEAP_SIZE hex - default 0x100000 if FLATTENED_DEVICE_TREE - default 0x4000 + default 0x100000 config STACK_SIZE hex diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index f3e2c4c..0fa999e 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -35,7 +35,4 @@ default 32 if SMM_TSEG default 4 -config HEAP_SIZE - default 0x8000 - endif diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig index 7f9300f..7bc3b0b 100644 --- a/src/mainboard/sifive/hifive-unleashed/Kconfig +++ b/src/mainboard/sifive/hifive-unleashed/Kconfig @@ -10,9 +10,6 @@ select FLATTENED_DEVICE_TREE select SPI_SDCARD -config HEAP_SIZE - default 0x10000 - config MAINBOARD_DIR default "sifive/hifive-unleashed" diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 3222198..57426b8 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -25,8 +25,4 @@ source "src/northbridge/amd/pi/00730F01/Kconfig" -config HEAP_SIZE - hex - default 0xc0000 - endif # NORTHBRIDGE_AMD_PI diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 09e04f3..8a738cf 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -182,11 +182,6 @@ hex default 0x800000 -#TODO: Check if the value of HEAP_SIZE is optimal -config HEAP_SIZE - hex - default 0x200000 - config ACPI_SSDT_PSD_INDEPENDENT bool "Allow core p-state independent transitions" default y diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f501398..42fe66f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -266,10 +266,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b823d02..e94c2f9 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -158,10 +158,6 @@ bool default n -config HEAP_SIZE - hex - default 0xc0000 - config EHCI_BAR hex default 0xfef00000 diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig index 5593685..7e48b5f 100644 --- a/src/soc/cavium/cn81xx/Kconfig +++ b/src/soc/cavium/cn81xx/Kconfig @@ -30,9 +30,6 @@ int default 1 -config HEAP_SIZE - default 0x10000 - config STACK_SIZE default 0x2000 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fd95f9e..e63bcd2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -216,11 +216,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - config GFX_GMA_DEFAULT_MMIO default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b22382b..aef9d85 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -255,10 +255,6 @@ help Name of file to store in the IFWI region. -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 6 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index a506b1b..92a99c4 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -177,10 +177,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config NHLT_DMIC_1CH_16B bool depends on ACPI_NHLT diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 7f1c767..3361c0d 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -104,10 +104,6 @@ hex default 0x0 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 7 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 624e362..9f70177 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -106,10 +106,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x8000 - config MAX_ROOT_PORTS int default 8 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 6dd6273..a471769 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -199,11 +199,6 @@ hex default 0x400000 -config HEAP_SIZE - hex - default 0x80000 if BMP_LOGO - default 0x10000 - # Intel recommends reserving the PCIe TBT root port resources as below: # - 42 buses # - 194 MiB Non-prefetchable memory diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d6a11363e..e0df501 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -151,10 +151,6 @@ help If you set this option to n, will not use native SD controller. -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 2c4715a..2d5cf08 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -152,10 +152,6 @@ config INTEL_TME default n -config HEAP_SIZE - hex - default 0x10000 - config MAX_ROOT_PORTS int default 24 if SOC_INTEL_TIGERLAKE_PCH_H diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 0931030..db3e5ad 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -94,10 +94,6 @@ config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION default y -config HEAP_SIZE - hex - default 0x80000 - config HPET_MIN_TICKS hex default 0x80 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index f54f771..ac166c3 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -71,10 +71,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index c2c3d4e..5d84387 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -55,10 +55,6 @@ hex default 0x7C00 -config HEAP_SIZE - hex - default 0x80000 - config IED_REGION_SIZE hex default 0x400000 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 5a21f47..bb88bec 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -80,10 +80,6 @@ hex default 0x8c00 -config HEAP_SIZE - hex - default 0x80000 - config STACK_SIZE hex default 0x4000 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 0eabb00..0ce9273 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -57,8 +57,4 @@ help Path for utils to combine SBL_ELF and bootblock -config HEAP_SIZE - hex - default 0x8000 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/80023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9 Gerrit-Change-Number: 80023 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/nissa/var/gothrax: Tune eMMC DLL values
by Subrata Banik (Code Review) 17 Jan '24

17 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79220?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/gothrax: Tune eMMC DLL values ...................................................................... mb/google/nissa/var/gothrax: Tune eMMC DLL values Gothrax cannot boot into OS with a kernel loading failure. Update eMMC DLL values to improve initialization reliability How to get these values: - Sending different speed TX/RX command/data signal to eMMC and check the response is successful or not. - Collecting above results from each eMMC model that project used. - Analysing logs to provide a fine tuned DLL values. BUG=b:310701323 TEST=Cold reboot stress test over 2500 cycles Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79220 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/gothrax/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index bb333aa..b36ff07 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -55,7 +55,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -66,13 +66,13 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004c" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10005" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. # Bit 2 - C1 has a redriver which does SBU muxing. -- To view, visit https://review.coreboot.org/c/coreboot/+/79220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie36cc9948e3d5dee46385e584baad141a249be79 Gerrit-Change-Number: 79220 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/elkhartlake: Drop redundant PcieRpEnable
by Jan Samek (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Lean Sheng Tan, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79921?usp=email ) Change subject: soc/intel/elkhartlake: Drop redundant PcieRpEnable ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Verified working on siemens/mc_ehl/mc_ehl1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa Gerrit-Change-Number: 79921 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 08:19:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/superiotool: reformat alternate dump output
by Arthur Heymans (Code Review) 17 Jan '24

17 Jan '24

Attention is currently required from: Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80004?usp=email ) Change subject: util/superiotool: reformat alternate dump output ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idef2cc136151328b114620eb297ab8fd62b71bcd Gerrit-Change-Number: 80004 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 17 Jan 2024 07:52:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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