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Change subject: mb/google/nissa/var/craaskov: Configure GPIOs according to schematics
......................................................................
Patch Set 12:
(2 comments)
File src/mainboard/google/brya/variants/craaskov/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/76636/comment/966b563a_1481dae1 :
PS11, Line 4: romstage-y += gpio.c
> no override when romstage.
No override, so remove it.
File src/mainboard/google/brya/variants/craaskov/gpio.c:
https://review.coreboot.org/c/coreboot/+/76636/comment/37588099_9a00af72 :
PS11, Line 68: static const struct pad_config romstage_gpio_table[] = {
> you can remove it if empty.
romstage_gpio_table is empty, so remove it.
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Hello Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel, Zheng Bao, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
......................................................................
util/amdfwtool: Deal with psp position in flash offset directly
It is based on work by Arthur Heymans, 69852.
Get rid of the confusing "position index" and use the relative flash
offset as the Kconfig setting instead.
TEST=binary identical on amd/birman amd/majolica amd/gardenia
amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon
pcengines/apu2
google/skyrim google/guybrush google/zork google/kahlee
(The test should be done with INCLUDE_CONFIG_FILE=n)
Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M configs/config.google_skyrim.no_video
M configs/config.google_skyrim.with_binaries
M src/mainboard/amd/chausie/Kconfig
M src/mainboard/amd/majolica/Kconfig
M src/mainboard/amd/mandolin/Kconfig
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/kahlee/Kconfig
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/zork/Kconfig
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/common/Makefile.inc
M src/soc/amd/common/block/include/amdblocks/psp_efs.h
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/Makefile.inc
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/Makefile.inc
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/Makefile.inc
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/fch.c
25 files changed, 125 insertions(+), 288 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/72939/23
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Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> d3hot […]
This actually depends on SSD FW. It would be good to test Hynix, Samsung etc. Anyway, d3hot should be fine for mainstream SSD.
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Change subject: mb/google/nissa/var/craaskov: Configure GPIOs according to schematics
......................................................................
mb/google/nissa/var/craaskov: Configure GPIOs according to schematics
Configure GPIOs based on schematics and confirm with EE.
BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com>
---
A src/mainboard/google/brya/variants/craaskov/Makefile.inc
A src/mainboard/google/brya/variants/craaskov/gpio.c
2 files changed, 82 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/76636/12
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Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> d3hot or d3cold here? will this effect another SSD?
d3hot
Rex and screebo using Micron (MTFDKBA512TFK & MTFDKBA512QFM respectively), these SSD having lower snoon/non-snoop LTRs (~5ms) and blocking S0i2.2 entry in MTL. Hence we need this feature (d3hot) as altername power management to avoid the Link state powermanager(as today). i.e. required for all SSD having lower LTR and blocking S0i2.2
Do to suggest to sane changes for all varients?
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Change subject: mb/google/dedede/var/cret: Generate new SPD ID for new memory parts
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Patch Set 3: Code-Review+2
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