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Hello Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: (wip)util/crossgcc: Update binutils from 2.40 to 2.41
......................................................................
(wip)util/crossgcc: Update binutils from 2.40 to 2.41
Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
D util/crossgcc/patches/binutils-2.40_stop_loosing_entry_point_when_LTO_enabled.patch
R util/crossgcc/patches/binutils-2.41_as-ipxe.patch
R util/crossgcc/patches/binutils-2.41_no-makeinfo.patch
D util/crossgcc/sum/binutils-2.40.tar.xz.cksum
A util/crossgcc/sum/binutils-2.41.tar.xz.cksum
6 files changed, 46 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/76852/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76864?usp=email )
Change subject: doc/forums: Update Matrix channel link
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76864/comment/c482e3e5_f0adea44 :
PS1, Line 9: Channel portalling has been disabled for the matrix.org-libera.chat
Maybe link to https://libera.chat/news/matrix-deportalling.
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Change subject: soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
......................................................................
Patch Set 13: Code-Review+2
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Hello Jakub Czapiga, Kangheui Won, Kapil Porwal, Subrata Banik, Tarun Tuli,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76835?usp=email
to look at the new patch set (#2).
Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................
mb/google/rex: enable d3hot for storage devices
_DSD "StorageD3Enable" property is needed to set under the root port in
the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt
D3hot support for storage devices.
Name (_DSD, Package () {
        ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
           Package () {
                Package (2) {"StorageD3Enable", 1},
// 1 - Enable; 0 - Disable
            }
        }
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/76835/2
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Hello Kangheui Won,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/76835?usp=email
to review the following change.
Change subject: mb/google/rex: enable d3hot for storage devices
......................................................................
mb/google/rex: enable d3hot for storage devices
_DSD "StorageD3Enable" property is needed to set under the root port in
the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt
D3hot support for storage devices.
Name (_DSD, Package () {
        ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
           Package () {
                Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable
            }
        }
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/76835/1
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index 793a46d..1435a7b 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -302,6 +302,13 @@
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)"
+ register "srcclk_pin" = "4"
+ device generic 0 on end
+ end
end #PCIE9 SSD card
device ref ish on
probe ISH ISH_ENABLE
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Change subject: mb/google/cyan: Drop I2C devices as wake sources
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Touchpad is wake source on chromebook. And we use GPE for that. cyan is pretty old boards not sure how they do this, hmm.
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