coreboot-gerrit August 2023

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[M] Change in coreboot[master]: cbfstool: Add relocation support for EFI binaries
by Jérémy Compostella (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Anil Kumar K, Cliff Huang, Jérémy Compostella, Subrata Banik. Hello Anil Kumar K, Cliff Huang, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76762?usp=email to look at the new patch set (#4). Change subject: cbfstool: Add relocation support for EFI binaries ...................................................................... cbfstool: Add relocation support for EFI binaries This patch allows EFI binaries stored in CBFS to be relocated at build time using the `--xip' option flag. It allows to include a Pre-EFI Initialization Module driver in CBFS and to execute it in pre-memory stages. Such a module could perform some platform specific initialization operations such as graphics initialization operations for instance. Change-Id: I5e98ffd1d864cf9ac675421471d888334d8ab28b Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/fsp_relocate.c M src/commonlib/include/commonlib/fsp.h M util/cbfstool/cbfstool.c 3 files changed, 56 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/76762/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e98ffd1d864cf9ac675421471d888334d8ab28b Gerrit-Change-Number: 76762 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller
by Eric Lai (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76829?usp=email ) Change subject: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Gerrit-Change-Number: 76829 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Aug 2023 00:29:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/intel/gma/Kconfig: Add VBT compression configuration entry
by Jérémy Compostella (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Anil Kumar K, Paul Menzel, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76816?usp=email ) Change subject: drivers/intel/gma/Kconfig: Add VBT compression configuration entry ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76816/comment/d83ef315_2ef462a9 : PS2, Line 12: > Tested how? What size and boot speed changes do you see on your test device? The intention of that patch is to allow to pick a different compression algorithm. But for my use-case it would be `none` as I would like to use the VBT in pre-memory stages (`romstage`). So the size and boot time impact is negative for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/76816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df6a96c2ec122f0ef8ee6a1e96ffbd621b14941 Gerrit-Change-Number: 76816 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Aug 2023 00:19:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
by Pratikkumar V Prajapati (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Tracy Wu. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76333?usp=email ) Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records ...................................................................... Patch Set 13: (1 comment) Patchset: PS12: > Can you please justify why the log is claiming there is a crash data available (in all power-cycle). […] I have pushed a patch https://review.coreboot.org/c/coreboot/+/76833, can you plz try with that? That patch is supposed to adjust size of Pmc crashlog issue. It might not be related to what you are seeing. But can you take all patches from this dependent patches and try again in your system. And attach the crashlog dump to the partner bug? -- To view, visit https://review.coreboot.org/c/coreboot/+/76333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Gerrit-Change-Number: 76333 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 00:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "util/amdfwtool: Add some PSP entries to both levels"
by Eric Lai (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Arthur Heymans, Martin L Roth, Matt DeVillier, Varshit Pandya. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76718?usp=email ) Change subject: Revert "util/amdfwtool: Add some PSP entries to both levels" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76718?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8042690af2764d6e46fe01287be598091b1a239 Gerrit-Change-Number: 76718 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 01 Aug 2023 00:14:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Skip crashlog region with metadata tag
by Pratikkumar V Prajapati (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Pratikkumar Prajapati, Subrata Banik, Tarun Tuli. Hello Pratikkumar Prajapati, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/76834?usp=email to review the following change. Change subject: soc/intel/meteorlake: Skip crashlog region with metadata tag ...................................................................... soc/intel/meteorlake: Skip crashlog region with metadata tag Region with metadata tag contains information about BDF entry for SOC PMC SRAM and IOE SRAM. We don't need to parse this as we already define BDFs in soc/pci_devs.h for these SRAMs. Also we need to skip to region as it does not contain any crashlog data. BUG=b:262501347 TEST=Able to build REX. Able to trigger crashlog and decode correctly. Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/76834/1 diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index e55b214..ce8ad54 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -125,8 +125,19 @@ if (!descriptor_table.regions[i].bits.size) continue; - + /* + * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM + * and IOE SRAM. We don't need to parse this as we already define BDFs in + * soc/pci_devs.h for these SRAMs. Also we need to skip to region as it does not + * contain any crashlog data + */ if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_META) { + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + } else if (descriptor_table.regions[i].bits.assign_tag == CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) { if (cl_copy_data_from_sram(pmc_sram_base, -- To view, visit https://review.coreboot.org/c/coreboot/+/76834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Gerrit-Change-Number: 76834 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/common: Add metadata tag definition for crashlog
by Pratikkumar V Prajapati (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Pratikkumar Prajapati. Hello Pratikkumar Prajapati, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/76833?usp=email to review the following change. Change subject: soc/intel/common: Add metadata tag definition for crashlog ...................................................................... soc/intel/common: Add metadata tag definition for crashlog When parsing descriptor table the record can have tag type = 7. This tag contains metadata depending on SOC. The platform may choose to parse it based on implementation of crashlog. BUG=b:262501347 TEST=Able to build REX. Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> --- M src/soc/intel/common/block/include/intelblocks/crashlog.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/76833/1 diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index 91e8edd..7d3252a 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -28,6 +28,7 @@ /* Tag field definitions */ #define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0 #define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1 +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_META 0x7 /* PMC crashlog discovery structs */ typedef union { -- To view, visit https://review.coreboot.org/c/coreboot/+/76833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Gerrit-Change-Number: 76833 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Attention: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2023