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Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/joxer/ramstage.c:
https://review.coreboot.org/c/coreboot/+/76773/comment/3502cd46_abf04323 :
PS3, Line 20: static void update_oem_variables(void)
> why don't you just put this in variant.c? IMHO, no need for extra file.
Done
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Hello Derek Huang, Felix Held, Ivan Chen, Scott Chao, Shou-Chieh Hsu, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76773?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+2 by Scott Chao, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables
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mb/google/nissa/var/joxer: support DPTF oem_variables
1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable.
2. Update passive policy and critical policy.
BUG=b:285477026
TEST=emerge-nissa coreboot and check the OEM variable.
Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com>
Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167
---
M src/mainboard/google/brya/variants/joxer/overridetree.cb
M src/mainboard/google/brya/variants/joxer/variant.c
2 files changed, 42 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/76773/4
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Change subject: mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)
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Patch Set 14: Code-Review+2
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Change subject: soc/intel/meteorlake: Exclude CBMEM region from TME encryption
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS4:
> Lets keep it separate, considering separate tests performed which is already detailed in commit message for both of these patches.
I don't see a point of having two CL (for same SOC) to enable configs which are interdependent. Assume those cls are landing separately and ended up adding into two different CPFE (by the builder) releases, then there would be one CPFE where CBMEM ranges (cbmem -c/-t, ramoops) are all encrypted and unable to access those range. The condition would be worse if ODM/OEM picked such CPFE for their SMT.
It would create unnecessarily trouble by the end of the day.
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