coreboot-gerrit August 2023

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[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Kopeć (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76418?usp=email ) Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... Patch Set 6: (2 comments) File src/soc/intel/alderlake/include/soc/vr_config.h: https://review.coreboot.org/c/coreboot/+/76418/comment/432a6791_85f78c71 : PS5, Line 12: /* > Ah, no. Thanks. File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/76418/comment/aec5c1a6_eb4e42e9 : PS6, Line 273: (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) > please, no spaces at the start of a line Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:04:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Żygowski (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Michał Kopeć, Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli. Hello Michał Kopeć, Paul Menzel, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76418?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Code-Review+2 by Michał Kopeć, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/vr_config.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/vr_config.c 5 files changed, 11 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/76418/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Enable RTD3 for SSD
by 9elements QA (Code Review) 01 Aug '23

01 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76831?usp=email ) Change subject: mb/google/rex/var/screebo: Enable RTD3 for SSD ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 4 / 12 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/175692 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/175691 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/175690 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/175689 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/175688 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/175687 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/175686 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/175685 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/175684 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/175683 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/175682 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/175681 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76831?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Gerrit-Change-Number: 76831 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 12:57:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: commonlib/tpm_log_serialized.h: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76841?usp=email ) Change subject: commonlib/tpm_log_serialized.h: Use C99 flexible arrays ...................................................................... commonlib/tpm_log_serialized.h: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/commonlib/include/commonlib/tpm_log_serialized.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/commonlib/include/commonlib/tpm_log_serialized.h b/src/commonlib/include/commonlib/tpm_log_serialized.h index 8372f94..26541cb 100644 --- a/src/commonlib/include/commonlib/tpm_log_serialized.h +++ b/src/commonlib/include/commonlib/tpm_log_serialized.h @@ -21,7 +21,7 @@ struct tpm_cb_log_table { uint16_t max_entries; uint16_t num_entries; - struct tpm_cb_log_entry entries[0]; /* Variable number of entries */ + struct tpm_cb_log_entry entries[]; /* Variable number of entries */ } __packed; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85 Gerrit-Change-Number: 76841 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: vendorcode/google: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76812?usp=email ) Change subject: vendorcode/google: Use C99 flexible arrays ...................................................................... vendorcode/google: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/google/chromeos/vpd_calibration.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/vendorcode/google/chromeos/vpd_calibration.c b/src/vendorcode/google/chromeos/vpd_calibration.c index e5f5b57..f66811f 100644 --- a/src/vendorcode/google/chromeos/vpd_calibration.c +++ b/src/vendorcode/google/chromeos/vpd_calibration.c @@ -39,7 +39,7 @@ */ struct calibration_entry { uint32_t size; - struct calibration_blob entries[0]; /* A varialble size container. */ + struct calibration_blob entries[]; /* A varialble size container. */ }; -- To view, visit https://review.coreboot.org/c/coreboot/+/76812?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06 Gerrit-Change-Number: 76812 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/acpi: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76813?usp=email ) Change subject: include/acpi: Use C99 flexible arrays ...................................................................... include/acpi: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I3d5838b825c6ac2a2959388381004993024081c3 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76813 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/acpi/acpi.h M src/include/acpi/acpi_ivrs.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index f1c52d1..0aa8026 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -506,7 +506,7 @@ uint16_t pci_segment_group; uint16_t iommu_info; uint32_t iommu_feature_info; - uint8_t entry[0]; + uint8_t entry[]; } __packed acpi_ivrs_ivhd_t; /* IVRS (I/O Virtualization Reporting Structure) Type 10h */ @@ -549,7 +549,7 @@ uint32_t efr_reg_image_low; uint32_t efr_reg_image_high; uint32_t reserved[2]; - uint8_t entry[0]; + uint8_t entry[]; } __packed acpi_ivrs_ivhd11_t; enum dev_scope_type { @@ -569,7 +569,7 @@ struct { u8 dev; u8 fn; - } __packed path[0]; + } __packed path[]; } __packed dev_scope_t; enum dmar_type { @@ -651,7 +651,7 @@ u8 host_address_width; u8 flags; u8 reserved[10]; - dmar_entry_t structure[0]; + dmar_entry_t structure[]; } __packed acpi_dmar_t; /* MADT: APIC Structure Types */ @@ -1246,7 +1246,7 @@ u32 revision; u32 table_size; u32 entry_count; - acpi_einj_action_table_t trigger_action[1]; + acpi_einj_action_table_t trigger_action[]; } __packed acpi_einj_trigger_table_t; typedef struct set_error_type { diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index fe0aa40..ad86e6a 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -201,7 +201,7 @@ uint32_t efr_reg_image_low; uint32_t efr_reg_image_high; uint32_t reserved[2]; - uint8_t entry[0]; + uint8_t entry[]; } __packed acpi_ivrs_ivhd40_t; typedef struct ivrs_ivhd_extended { -- To view, visit https://review.coreboot.org/c/coreboot/+/76813?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5838b825c6ac2a2959388381004993024081c3 Gerrit-Change-Number: 76813 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
by Kapil Porwal (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Tracy Wu. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76333?usp=email ) Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records ...................................................................... Patch Set 13: (1 comment) Patchset: PS12: > I have pushed a patch https://review.coreboot. […] I am seeing below messages with all 5 CLs - ``` ... [DEBUG] crashlog size:pmc-0x0, ioe-pmc-0x0 cpu-0x2000 [DEBUG] crashlog size:pmc-0x0, ioe-pmc-0x0 cpu-0x2000 [DEBUG] crashlog size:pmc-0x0, ioe-pmc-0x0 cpu-0x2000 [DEBUG] cl_data 0x75b5807c, cpu_record_size 0x2000 [DEBUG] CPU crash data collection. [DEBUG] ACPI: * BERT ``` I will attached the dump to the partner bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/76333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Gerrit-Change-Number: 76333 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 12:55:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/broadwell/include/soc/me.h: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76837?usp=email ) Change subject: soc/intel/broadwell/include/soc/me.h: Use C99 flexible arrays ...................................................................... soc/intel/broadwell/include/soc/me.h: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/broadwell/include/soc/me.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h index b0c50a2..959290d 100644 --- a/src/soc/intel/broadwell/include/soc/me.h +++ b/src/soc/intel/broadwell/include/soc/me.h @@ -429,7 +429,7 @@ u8 icc_profile_index; u8 reserved; u32 icc_reg_bundles; - icc_address_mask icc_address_mask[0]; + icc_address_mask icc_address_mask[]; } __packed mbp_icc_profile; typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/76837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a Gerrit-Change-Number: 76837 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/common/mma: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76836?usp=email ) Change subject: soc/intel/common/mma: Use C99 flexible arrays ...................................................................... soc/intel/common/mma: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Id19193b960935eeffca8e8db60073321592368fe Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/mma.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c index 3314e8e..6501f11 100644 --- a/src/soc/intel/common/mma.c +++ b/src/soc/intel/common/mma.c @@ -17,7 +17,7 @@ struct mma_data_container { uint32_t mma_signature; /* "MMAD" */ - uint8_t mma_data[0]; /* Variable size, platform/run time dependent. */ + uint8_t mma_data[]; /* Variable size, platform/run time dependent. */ } __packed; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/76836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id19193b960935eeffca8e8db60073321592368fe Gerrit-Change-Number: 76836 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76815?usp=email ) Change subject: util: Use C99 flexible arrays ...................................................................... util: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I6b87680ec9f501945ae266ae4e4927efd2399d56 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76815 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/cbfstool/ifwitool.c M util/cbmem/cbmem.c M util/intelvbttool/intelvbttool.c M util/nvramtool/coreboot_tables.h 4 files changed, 7 insertions(+), 7 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c index efcb594..453d85c 100644 --- a/util/cbfstool/ifwitool.c +++ b/util/cbfstool/ifwitool.c @@ -70,7 +70,7 @@ struct bpdt { struct bpdt_header h; /* In practice, this could be an array of 0 to n entries. */ - struct bpdt_entry e[0]; + struct bpdt_entry e[]; } __packed; static inline size_t get_bpdt_size(struct bpdt_header *h) @@ -124,7 +124,7 @@ struct subpart_dir { struct subpart_dir_header h; /* In practice, this could be an array of 0 to n entries. */ - struct subpart_dir_entry e[0]; + struct subpart_dir_entry e[]; } __packed; static inline size_t subpart_dir_size(struct subpart_dir_header *h) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 73c410c..d33b714 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1116,7 +1116,7 @@ struct cbmem_console { u32 size; u32 cursor; - u8 body[0]; + u8 body[]; } __attribute__ ((__packed__)); #define CBMC_CURSOR_MASK ((1 << 28) - 1) diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index c8d7a08..a70b33c 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -157,7 +157,7 @@ * number = (block_size - sizeof(bdb_general_definitions))/ * sizeof(child_device_config); */ - struct common_child_dev_config devices[0]; + struct common_child_dev_config devices[]; } __attribute__ ((packed)); struct bdb_driver_features { diff --git a/util/nvramtool/coreboot_tables.h b/util/nvramtool/coreboot_tables.h index aafeab4..d4db00c 100644 --- a/util/nvramtool/coreboot_tables.h +++ b/util/nvramtool/coreboot_tables.h @@ -90,7 +90,7 @@ struct lb_memory { uint32_t tag; uint32_t size; - struct lb_memory_range map[0]; + struct lb_memory_range map[]; }; #define LB_TAG_HWRPB 0x0002 @@ -106,7 +106,7 @@ uint32_t size; uint8_t vendor_idx; uint8_t part_number_idx; - uint8_t strings[0]; + uint8_t strings[]; }; #define LB_TAG_VERSION 0x0004 @@ -122,7 +122,7 @@ struct lb_string { uint32_t tag; uint32_t size; - uint8_t string[0]; + uint8_t string[]; }; #define LB_TAG_SERIAL 0x000f #define LB_TAG_CONSOLE 0x0010 -- To view, visit https://review.coreboot.org/c/coreboot/+/76815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b87680ec9f501945ae266ae4e4927efd2399d56 Gerrit-Change-Number: 76815 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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