coreboot-gerrit August 2023

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[S] Change in coreboot[master]: payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76851?usp=email ) Change subject: payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays ...................................................................... payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76851 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/include/coreboot_tables.h 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 5f6a223..4502e34 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -125,7 +125,7 @@ struct cb_memory { u32 tag; u32 size; - struct cb_memory_range map[0]; + struct cb_memory_range map[]; }; struct cb_hwrpb { @@ -139,7 +139,7 @@ u32 size; u8 vendor_idx; u8 part_number_idx; - u8 strings[0]; + u8 strings[]; }; enum type_c_orientation { @@ -166,13 +166,13 @@ struct type_c_info { u32 port_count; - struct type_c_port_info port_info[0]; + struct type_c_port_info port_info[]; }; struct cb_string { u32 tag; u32 size; - u8 string[0]; + u8 string[]; }; struct cb_serial { @@ -255,7 +255,7 @@ u32 size; u32 count; - struct cb_gpio gpios[0]; + struct cb_gpio gpios[]; }; struct cb_pcie { @@ -305,7 +305,7 @@ * space and host address space. This determines the number of entries in mmap_table. */ uint32_t mmap_count; - struct flash_mmap_window mmap_table[0]; + struct flash_mmap_window mmap_table[]; }; struct cb_boot_media_params { @@ -344,7 +344,7 @@ uint32_t tag; uint32_t size; uint32_t count; - struct mac_address mac_addrs[0]; + struct mac_address mac_addrs[]; }; struct cb_mmc_info { -- To view, visit https://review.coreboot.org/c/coreboot/+/76851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c Gerrit-Change-Number: 76851 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common: Redefine EFS_OFFSET
by Fred Reitberger (Code Review) 01 Aug '23

01 Aug '23

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76764?usp=email ) Change subject: soc/amd/common: Redefine EFS_OFFSET ...................................................................... soc/amd/common: Redefine EFS_OFFSET The EFS_OFFSET is the relative address to flash base. We can not assume the flash size is 16M. The change will affect only Gardenia and Pademelon whose flash size are 8M. Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764 Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/psp_efs.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/psp_efs.h b/src/soc/amd/common/block/include/amdblocks/psp_efs.h index 1608ce5..a930bc9 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp_efs.h +++ b/src/soc/amd/common/block/include/amdblocks/psp_efs.h @@ -6,7 +6,7 @@ #include <types.h> -#define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1) +#define EFS_OFFSET (CONFIG_ROM_SIZE - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000) #define EMBEDDED_FW_SIGNATURE 0x55aa55aa -- To view, visit https://review.coreboot.org/c/coreboot/+/76764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Gerrit-Change-Number: 76764 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/nissa/var/joxer: support DPTF oem_variables
by Eric Lai (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Derek Huang, Felix Held, Ivan Chen, Mark Hsieh, Scott Chao, Shou-Chieh Hsu, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76773?usp=email ) Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/mainboard/google/brya/variants/joxer/variant.c: https://review.coreboot.org/c/coreboot/+/76773/comment/9206766d_99486a19 : PS4, Line 9: #include <device/pci.h> nit: header should in alphabet order -- To view, visit https://review.coreboot.org/c/coreboot/+/76773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Gerrit-Change-Number: 76773 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:53:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Enable RTD3 for SSD
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76831?usp=email ) Change subject: mb/google/rex/var/screebo: Enable RTD3 for SSD ...................................................................... mb/google/rex/var/screebo: Enable RTD3 for SSD Currently, S0iX test is failing because S0i2 susbstate is blocked. Enable RTD3 for SSD to unblock S0i2.2 substate residency. BUG=none TEST=Screebo can enter into S0iX. S0iX substate residency w/o this CL - ``` Substate Residency S0i2.0 0 S0i2.1 38451594 S0i2.2 0 ``` S0iX substate residency w/ this CL - ``` Substate Residency S0i2.0 0 S0i2.1 12108 S0i2.2 33878424 ``` Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 4567d5d..a7b7d54 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -231,6 +231,13 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "4" + device generic 0 on end + end end # PCIE4_P9 SSD card device ref pcie_rp10 on # Enable SD Card PCIE4 rp10 using clk 7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76831?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Gerrit-Change-Number: 76831 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Jakub Czapiga has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76829?usp=email ) Change subject: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller ...................................................................... mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller Restrict ASPM to L1 for SD controller to avoid AERs. BUG=b:288830220 TEST=No PCIE AER on SD controller on Screebo. w/o this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- ~ # dmesg | grep -i -e "pci.*error" [ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0 ``` w/ this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # dmesg | grep -i -e "pci.*error" ``` Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Jakub Czapiga: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 67bc4f8..4567d5d 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -238,6 +238,7 @@ .clk_src = 7, .clk_req = 7, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" -- To view, visit https://review.coreboot.org/c/coreboot/+/76829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Gerrit-Change-Number: 76829 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76829?usp=email ) Change subject: mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Gerrit-Change-Number: 76829 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:52:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Kapil Porwal, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Tracy Wu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76333?usp=email ) Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records ...................................................................... Patch Set 13: (3 comments) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/76333/comment/d8e6568c_72360cff : PS13, Line 381: 0x%x info-nit: You can use `%#x` instead of `0x%x`, or `%#X` instead of `%#X`. https://review.coreboot.org/c/coreboot/+/76333/comment/49e47693_41626d3a : PS13, Line 403: printk(BIOS_DEBUG, "cpu crashlog records already consumed." : "id: 0x%x dw0: 0x%x\n", i, dw0); Message says `records` but only one ID is passed. Can you rephrase this message to inform that all records from this one ID are already consumed instead? File src/soc/intel/meteorlake/include/soc/crashlog.h: https://review.coreboot.org/c/coreboot/+/76333/comment/f1f5f303_07f4597d : PS13, Line 21: 0x1 `(1 << 31)` should be enough here or you can use `BIT(31)` from `types.h` instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/76333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Gerrit-Change-Number: 76333 Gerrit-PatchSet: 13 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Adjust discovery table offset based on CPUID
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Kapil Porwal, Paul Menzel, Pratikkumar V Prajapati, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, Tracy Wu. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76400?usp=email ) Change subject: soc/intel/meteorlake: Adjust discovery table offset based on CPUID ...................................................................... Patch Set 11: (3 comments) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/76400/comment/4ce5ca96_1f58bc67 : PS11, Line 358: u32 bar_addr = 0, disc_tab_addr = 0, disc_tab_offset = 0; code-style: AFAIK we are using C11 (`-std=gnu11`), so variable declarations are not required to be at the beginning of the function. Can we get rid of unnecessary lines like this one and declare&define variables in line they are first assigned (if feasible)? https://review.coreboot.org/c/coreboot/+/76400/comment/a970fba6_096d0ddd : PS11, Line 367: disc_tab_offset <<= 3; Is there a risk of overflow in this operation? https://review.coreboot.org/c/coreboot/+/76400/comment/4c3b24a4_1986e789 : PS11, Line 374: cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + : ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); : Shouldn't it be binary-OR instead of addition? (Just asking for clarification :) ) -- To view, visit https://review.coreboot.org/c/coreboot/+/76400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90647fb6190a52b42298398263978beaf931b035 Gerrit-Change-Number: 76400 Gerrit-PatchSet: 11 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:34:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google: Add more comment on GFX devices for the future reference
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli, Won Chung. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76776?usp=email ) Change subject: mb/google: Add more comment on GFX devices for the future reference ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/mainboard/google/rex/variants/rex0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76776/comment/2ac563b2_9147e134 : PS4, Line 164: nit: "is enumerated" Same for all other occurrences of this sentence in CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/76776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Gerrit-Change-Number: 76776 Gerrit-PatchSet: 4 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:28:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Allow mainboard to configure c1-state auto-demo...
by Jakub Czapiga (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Sukumar Ghorai, Tarun Tuli. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76826?usp=email ) Change subject: soc/intel/meteorlake: Allow mainboard to configure c1-state auto-demotion ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc Gerrit-Change-Number: 76826 Gerrit-PatchSet: 3 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 11:24:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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