coreboot-gerrit August 2023

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[XS] Change in coreboot[master]: libpayload/drivers/cbmem_console: Use C99 flexible arrays
by 9elements QA (Code Review) 01 Aug '23

01 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76849?usp=email ) Change subject: libpayload/drivers/cbmem_console: Use C99 flexible arrays ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 4 / 12 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/175728 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/175727 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/175726 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/175725 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/175724 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/175723 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/175722 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/175721 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/175720 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/175719 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/175718 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/175717 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76849?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fd3f068ff731e1d9fed7c38ba6815e1eed86450 Gerrit-Change-Number: 76849 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:52:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/joxer: support DPTF oem_variables
by Eric Lai (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Derek Huang, Felix Held, Ivan Chen, Mark Hsieh, Scott Chao, Shou-Chieh Hsu, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76773?usp=email ) Change subject: mb/google/nissa/var/joxer: support DPTF oem_variables ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Gerrit-Change-Number: 76773 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:51:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/usb/ehci.h: Use C99 flexible arrays
by Felix Held (Code Review) 01 Aug '23

01 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76840?usp=email ) Change subject: drivers/usb/ehci.h: Use C99 flexible arrays ...................................................................... drivers/usb/ehci.h: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/drivers/usb/ehci.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index b9054cfb..3feab86 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -97,7 +97,7 @@ #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ /* PORTSC: offset 0x44 */ - u32 port_status[0]; /* up to N_PORTS */ + u32 port_status[]; /* up to N_PORTS */ /* EHCI 1.1 addendum */ #define PORTSC_SUSPEND_STS_ACK 0 #define PORTSC_SUSPEND_STS_NYET 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/76840?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1 Gerrit-Change-Number: 76840 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays
by 9elements QA (Code Review) 01 Aug '23

01 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76851?usp=email ) Change subject: payloads/libpayload/include/coreboot_tables: Use C99 flexible arrays ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 4 / 12 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/175716 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/175715 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/175714 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/175713 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/175712 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/175711 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/175710 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/175709 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/175708 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/175707 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/175706 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/175705 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76851?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf3da1b0a0666769ae7b5d5f641b85436b324b4c Gerrit-Change-Number: 76851 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:38:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: linux_trampoline: Handle coreboot framebuffer
by Felix Held (Code Review) 01 Aug '23

01 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76431?usp=email ) Change subject: linux_trampoline: Handle coreboot framebuffer ...................................................................... linux_trampoline: Handle coreboot framebuffer Translate the coreboot framebuffer info from coreboot tables to the Linux zero page. Tested in QEMU/Q35 with a kernel w/ efifb enabled. Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff Signed-off-by: Nico Huber <nico.h(a)gmx.de> Co-authored-by: Bill XIE <persmule(a)hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76431 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Reviewed-by: Samuel Holland <samuel(a)sholland.org> Reviewed-by: Bill XIE <persmule(a)hardenedlinux.org> --- M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 2 files changed, 43 insertions(+), 9 deletions(-) Approvals: Bill XIE: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Samuel Holland: Looks good to me, but someone else must approve Nico Huber: Looks good to me, but someone else must approve diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 767c8be..d36e60d 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -102,7 +102,36 @@ .testFramebuffer: cmp $CB_TAG_FRAMEBUFFER, (%ebx) jne .endScan -/* TODO: handle framebuffer tag */ + +cmpl $0, 0x0c(%ebx) /* check if upper 32-bit of framebuffer address are 0 */ +jne .endScan + +mov $LINUX_PARAM_LOC, %edi /* translate the framebuffer entry into Linux' struct screen_info */ +mov 0x08(%ebx), %eax /* physical_address */ +mov %eax, 0x18(%edi) /* -> lfb_base */ +mov 0x10(%ebx), %eax /* x_resolution */ +mov %ax, 0x12(%edi) /* -> lfb_width */ +mov 0x14(%ebx), %eax /* y_resolution */ +mov %ax, 0x14(%edi) /* -> lfb_height */ +mov 0x18(%ebx), %edx /* bytes_per_line */ +mov %dx, 0x24(%edi) /* -> lfb_linelength */ + +mul %edx /* bytes_per_line * y_resolution */ +mov %eax, 0x1c(%edi) /* -> lfb_size */ + +movzbw 0x1c(%ebx), %ax /* bits_per_pixel */ +mov %ax, 0x16(%edi) /* -> lfb_depth */ + +mov $4, %esi /* Copy 4 color components' pos and size, each 1 byte. */ +1: +mov 0x1b(%ebx, %esi, 2), %ax +rol %ax /* Order is reversed for Linux, hence swap. */ +mov %ax, 0x24(%edi, %esi, 2) +dec %esi +jnz 1b + +#define LFB_EFI_SIMPLE 0x70 /* VIDEO_TYPE_EFI in Linux */ +movb $LFB_EFI_SIMPLE, 0x0f(%edi) /* -> orig_video_isVGA */ .endScan: add 4(%ebx), %ebx diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index 46bb800..87c595a 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -3,18 +3,23 @@ unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, - 0xcb, 0x0f, 0x84, 0xc5, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, + 0xcb, 0x0f, 0x84, 0x12, 0x01, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x53, 0x8b, 0x43, 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0x89, 0xc6, 0xbf, 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, 0x00, 0x89, 0xf0, 0x91, 0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xa1, - 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x2f, 0x83, 0x7f, + 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x7c, 0x83, 0x7f, 0x10, 0x0c, 0x7e, 0x07, 0xc7, 0x47, 0x10, 0x02, 0x00, 0x00, 0x00, 0x48, 0x83, 0xc7, 0x14, 0xeb, 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x12, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, - 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0xeb, 0x05, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, - 0x49, 0x0f, 0x85, 0x78, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, - 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, - 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, - 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd + 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0xeb, 0x52, 0x83, 0x3b, 0x12, 0x75, 0x4d, 0x83, 0x7b, 0x0c, + 0x00, 0x75, 0x47, 0xbf, 0x00, 0x00, 0x09, 0x00, 0x8b, 0x43, 0x08, 0x89, 0x47, 0x18, 0x8b, 0x43, + 0x10, 0x66, 0x89, 0x47, 0x12, 0x8b, 0x43, 0x14, 0x66, 0x89, 0x47, 0x14, 0x8b, 0x53, 0x18, 0x66, + 0x89, 0x57, 0x24, 0xf7, 0xe2, 0x89, 0x47, 0x1c, 0x66, 0x0f, 0xb6, 0x43, 0x1c, 0x66, 0x89, 0x47, + 0x16, 0xbe, 0x04, 0x00, 0x00, 0x00, 0x66, 0x8b, 0x44, 0x73, 0x1b, 0x66, 0xd1, 0xc0, 0x66, 0x89, + 0x44, 0x77, 0x24, 0x4e, 0x75, 0xf0, 0xc6, 0x47, 0x0f, 0x70, 0x03, 0x5b, 0x04, 0x49, 0x0f, 0x85, + 0x2b, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, 0x00, + 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, + 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, 0x00, + 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd }; -unsigned int trampoline_len = 239; +unsigned int trampoline_len = 316; -- To view, visit https://review.coreboot.org/c/coreboot/+/76431?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2447b2366df8dd8ffe741c943de544d8b4d02dff Gerrit-Change-Number: 76431 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: insurgo(a)riseup.net Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 ms
by Felix Held (Code Review) 01 Aug '23

01 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76766?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 ms ...................................................................... drivers/mipi: sta_ili9882t: Change TReset-CMD from 1.1 ms to 20 ms In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence, the TReset-CMD (Reset to First Command in Display Sleep In Mode) should be larger than 10ms, but it's 1.1ms now. This may cause abnormal display as some commands may be lost during power on. Fix this and leave some margins by increasing TReset-CMD to 20ms. Also, to align with the kernel driver structure starry_ili9882t_init_cmd, add 20ms delay at the end of command. [1] ILI9882T_Datasheet_20220428.pdf BUG=b:293380212 TEST=Boot and display normally Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766 Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/drivers/mipi/panel-STA_ILI9882T.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: cong yang: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve diff --git a/src/drivers/mipi/panel-STA_ILI9882T.c b/src/drivers/mipi/panel-STA_ILI9882T.c index 51f01e5..2514642 100644 --- a/src/drivers/mipi/panel-STA_ILI9882T.c +++ b/src/drivers/mipi/panel-STA_ILI9882T.c @@ -19,6 +19,7 @@ }, }, .init = { + PANEL_DELAY(20), PANEL_DCS(0xFF, 0x98, 0x82, 0x01), PANEL_DCS(0x00, 0x42), PANEL_DCS(0x01, 0x11), @@ -325,5 +326,6 @@ PANEL_DCS(0x11), PANEL_DELAY(120), PANEL_DCS(0x29), + PANEL_DELAY(20), }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/76766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc Gerrit-Change-Number: 76766 Gerrit-PatchSet: 6 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Douglas Anderson <dianders(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: lib/gcov-io.h: Use C99 flexible arrays
by Felix Held (Code Review) 01 Aug '23

01 Aug '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76846?usp=email ) Change subject: lib/gcov-io.h: Use C99 flexible arrays ...................................................................... lib/gcov-io.h: Use C99 flexible arrays Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76846 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/lib/gcov-io.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/lib/gcov-io.h b/src/lib/gcov-io.h index 14524248..af2d292 100644 --- a/src/lib/gcov-io.h +++ b/src/lib/gcov-io.h @@ -443,7 +443,7 @@ gcov_unsigned_t ident; /* unique ident of function */ gcov_unsigned_t lineno_checksum; /* function lineo_checksum */ gcov_unsigned_t cfg_checksum; /* function cfg checksum */ - struct gcov_ctr_info ctrs[0]; /* instrumented counters */ + struct gcov_ctr_info ctrs[]; /* instrumented counters */ }; /* Type of function used to merge counters. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/76846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff Gerrit-Change-Number: 76846 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common: Redefine EFS_OFFSET
by 9elements QA (Code Review) 01 Aug '23

01 Aug '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76764?usp=email ) Change subject: soc/amd/common: Redefine EFS_OFFSET ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 4 / 12 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/175704 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/175703 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/175702 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/175701 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/175700 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/175699 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/175698 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/175697 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/175696 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/175695 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/175694 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/175693 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1 Gerrit-Change-Number: 76764 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:20:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Żygowski (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli. Hello Michał Kopeć, Paul Menzel, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76418?usp=email to look at the new patch set (#7). Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO Only the headers on Intel FSP repository have the CnviWifiCore present. Options guarded for RPL like: DisableDynamicTccoldHandshake or EnableFastVmode and IccLimit is also supported by all public FSPs (except ADL-N for the handshake). Options like LowerBasicMemTestSize and DisableSagvReorder have to be guarded when FSP_USE_REPO is not selected, as publci FSPs do not have these options. Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE as dependency on the guarded UPDs to make them available for FSPs that support them as well. Also prioritize the headers from FSP repo over vendorcode headers if FSP_USE_REPO is selected. Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/vr_config.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/vr_config.c 5 files changed, 11 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/76418/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
by Michał Kopeć (Code Review) 01 Aug '23

01 Aug '23

Attention is currently required from: Michał Żygowski, Paul Menzel, Subrata Banik, Tarun Tuli. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76418?usp=email ) Change subject: soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO ...................................................................... Patch Set 6: (2 comments) File src/soc/intel/alderlake/include/soc/vr_config.h: https://review.coreboot.org/c/coreboot/+/76418/comment/432a6791_85f78c71 : PS5, Line 12: /* > Ah, no. Thanks. File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/76418/comment/aec5c1a6_eb4e42e9 : PS6, Line 273: (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO)) > please, no spaces at the start of a line Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/76418?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8 Gerrit-Change-Number: 76418 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Aug 2023 13:04:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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