coreboot-gerrit May 2023

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74844 ) Change subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Gerrit-Change-Number: 74844 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 16:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/mainboard/rex: Perform CSE FW update in RAMSTAGE
by Anil Kumar K (Code Review) 01 May '23

01 May '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74764 to look at the new patch set (#6). Change subject: src/mainboard/rex: Perform CSE FW update in RAMSTAGE ...................................................................... src/mainboard/rex: Perform CSE FW update in RAMSTAGE TEST=Build and boot google/rex board. Check CSE FW update is successful. BRANCH=None BUG=b:273207144 Change-Id: I36e59b0c61e852d5c3b7357292039211fcdbb0aa Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74764/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e59b0c61e852d5c3b7357292039211fcdbb0aa Gerrit-Change-Number: 74764 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Tim Van Patten (Code Review) 01 May '23

01 May '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 15:34:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Kconfig: Group dependency on X86EMU_DEBUG
by Elyes Haouas (Code Review) 01 May '23

01 May '23

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74901 ) Change subject: Kconfig: Group dependency on X86EMU_DEBUG ...................................................................... Kconfig: Group dependency on X86EMU_DEBUG Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74901/1 diff --git a/src/Kconfig b/src/Kconfig index 50381ae..f8d7f76 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1093,10 +1093,11 @@ If unsure, say N. +if X86EMU_DEBUG + config X86EMU_DEBUG_JMP bool "Trace JMP/RETF" default n - depends on X86EMU_DEBUG help Print information about JMP and RETF opcodes from x86emu. @@ -1107,7 +1108,6 @@ config X86EMU_DEBUG_TRACE bool "Trace all opcodes" default n - depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. @@ -1120,7 +1120,6 @@ config X86EMU_DEBUG_PNP bool "Log Plug&Play accesses" default n - depends on X86EMU_DEBUG help Print Plug And Play accesses made by option ROMs. @@ -1131,7 +1130,6 @@ config X86EMU_DEBUG_DISK bool "Log Disk I/O" default n - depends on X86EMU_DEBUG help Print Disk I/O related messages. @@ -1142,7 +1140,6 @@ config X86EMU_DEBUG_PMM bool "Log PMM" default n - depends on X86EMU_DEBUG help Print messages related to POST Memory Manager (PMM). @@ -1154,7 +1151,6 @@ config X86EMU_DEBUG_VBE bool "Debug VESA BIOS Extensions" default n - depends on X86EMU_DEBUG help Print messages related to VESA BIOS Extension (VBE) functions. @@ -1165,7 +1161,6 @@ config X86EMU_DEBUG_INT10 bool "Redirect INT10 output to console" default n - depends on X86EMU_DEBUG help Let INT10 (i.e. character output) calls print messages to debug output. @@ -1176,7 +1171,6 @@ config X86EMU_DEBUG_INTERRUPTS bool "Log intXX calls" default n - depends on X86EMU_DEBUG help Print messages related to interrupt handling. @@ -1187,7 +1181,6 @@ config X86EMU_DEBUG_CHECK_VMEM_ACCESS bool "Log special memory accesses" default n - depends on X86EMU_DEBUG help Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors) @@ -1199,7 +1192,6 @@ config X86EMU_DEBUG_MEM bool "Log all memory accesses" default n - depends on X86EMU_DEBUG help Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions. @@ -1211,7 +1203,6 @@ config X86EMU_DEBUG_IO bool "Log IO accesses" default n - depends on X86EMU_DEBUG help Print I/O accesses made by option ROM. @@ -1222,12 +1213,14 @@ config X86EMU_DEBUG_TIMINGS bool "Output timing information" default n - depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER + depends on HAVE_MONOTONIC_TIMER help Print timing information needed by i915tool. If unsure, say N. +endif + config DEBUG_SPI_FLASH bool "Output verbose SPI flash debug messages" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/74901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8 Gerrit-Change-Number: 74901 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/jasperlake: Enable early caching of RAMTOP region
by Subrata Banik (Code Review) 01 May '23

01 May '23

Attention is currently required from: Sean Rhodes, Matt DeVillier. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74518 ) Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74518/comment/b0162b10_b2ab1e29 PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of : 16MB) > same Q as with CML, how does this affect boards with a 32MB flash? should be applicable for all Intel platform where the BIOS region(16MB) can be cached. -- To view, visit https://review.coreboot.org/c/coreboot/+/74518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Gerrit-Change-Number: 74518 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 May 2023 15:18:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74853 ) Change subject: mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections ...................................................................... mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name 2 files changed, 82 insertions(+), 69 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index c4d6f4a..1e694c6 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -27,26 +27,49 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS + select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50 select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50 - select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE + select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_TI50 if BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 +config BOARD_GOOGLE_CHRONICLER + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_COLLIS + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_COPANO + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_DELBIN select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_DROBIT + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_ELDRID select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_ELEMI + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_HALVOR select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM @@ -74,6 +97,15 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM +config BOARD_GOOGLE_VOEMA + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOLET + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_VOLTEER select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM @@ -101,38 +133,6 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES -config BOARD_GOOGLE_ELEMI - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_VOEMA - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - select VARIANT_HAS_MIPI_CAMERA - -config BOARD_GOOGLE_DROBIT - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select DRIVERS_GENESYSLOGIC_GL9755 - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_COPANO - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_COLLIS - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_VOLET - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_CHRONICLER - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS @@ -189,50 +189,50 @@ default "Google_Volteer" config MAINBOARD_PART_NUMBER + default "Chronicler" if BOARD_GOOGLE_CHRONICLER + default "Collis" if BOARD_GOOGLE_COLLIS + default "Copano" if BOARD_GOOGLE_COPANO default "Delbin" if BOARD_GOOGLE_DELBIN + default "Drobit" if BOARD_GOOGLE_DROBIT default "Eldrid" if BOARD_GOOGLE_ELDRID + default "Elemi" if BOARD_GOOGLE_ELEMI default "Halvor" if BOARD_GOOGLE_HALVOR default "Lindar" if BOARD_GOOGLE_LINDAR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Terrador" if BOARD_GOOGLE_TERRADOR default "Todor" if BOARD_GOOGLE_TODOR default "Trondo" if BOARD_GOOGLE_TRONDO + default "Voema" if BOARD_GOOGLE_VOEMA + default "Volet" if BOARD_GOOGLE_VOLET default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL - default "Elemi" if BOARD_GOOGLE_ELEMI - default "Voema" if BOARD_GOOGLE_VOEMA - default "Drobit" if BOARD_GOOGLE_DROBIT - default "Copano" if BOARD_GOOGLE_COPANO - default "Collis" if BOARD_GOOGLE_COLLIS - default "Volet" if BOARD_GOOGLE_VOLET - default "Chronicler" if BOARD_GOOGLE_CHRONICLER config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) config VARIANT_DIR + default "chronicler" if BOARD_GOOGLE_CHRONICLER + default "collis" if BOARD_GOOGLE_COLLIS + default "copano" if BOARD_GOOGLE_COPANO default "delbin" if BOARD_GOOGLE_DELBIN + default "drobit" if BOARD_GOOGLE_DROBIT default "eldrid" if BOARD_GOOGLE_ELDRID + default "elemi" if BOARD_GOOGLE_ELEMI default "halvor" if BOARD_GOOGLE_HALVOR default "lindar" if BOARD_GOOGLE_LINDAR default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR default "todor" if BOARD_GOOGLE_TODOR default "trondo" if BOARD_GOOGLE_TRONDO + default "voema" if BOARD_GOOGLE_VOEMA + default "volet" if BOARD_GOOGLE_VOLET default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL - default "elemi" if BOARD_GOOGLE_ELEMI - default "voema" if BOARD_GOOGLE_VOEMA - default "drobit" if BOARD_GOOGLE_DROBIT - default "copano" if BOARD_GOOGLE_COPANO - default "collis" if BOARD_GOOGLE_COLLIS - default "volet" if BOARD_GOOGLE_VOLET - default "chronicler" if BOARD_GOOGLE_CHRONICLER config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d868e52..9ee1bec 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,11 +1,26 @@ comment "Volteer" +config BOARD_GOOGLE_CHRONICLER + bool "-> Chronicler" + +config BOARD_GOOGLE_COLLIS + bool "-> Collis" + +config BOARD_GOOGLE_COPANO + bool "-> Copano (ASUS Chromebook Flip CX5400)" + config BOARD_GOOGLE_DELBIN bool "-> Delbin (ASUS Chromebook Flip CX5)" +config BOARD_GOOGLE_DROBIT + bool "-> Drobit (ASUS Chromebook CX9400)" + config BOARD_GOOGLE_ELDRID bool "-> Eldrid" +config BOARD_GOOGLE_ELEMI + bool "-> Elemi (HP Pro c640 G2 Chromebook)" + config BOARD_GOOGLE_HALVOR bool "-> Halvor" @@ -24,6 +39,12 @@ config BOARD_GOOGLE_TRONDO bool "-> Trondo" +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + +config BOARD_GOOGLE_VOLET + bool "-> Volet" + config BOARD_GOOGLE_VOLTEER bool "-> Volteer" @@ -36,24 +57,3 @@ config BOARD_GOOGLE_VOXEL bool "-> Voxel (Acer Chromebook Spin 713 (CP713-3W))" - -config BOARD_GOOGLE_ELEMI - bool "-> Elemi (HP Pro c640 G2 Chromebook)" - -config BOARD_GOOGLE_VOEMA - bool "-> Voema" - -config BOARD_GOOGLE_DROBIT - bool "-> Drobit (ASUS Chromebook CX9400)" - -config BOARD_GOOGLE_COPANO - bool "-> Copano (ASUS Chromebook Flip CX5400)" - -config BOARD_GOOGLE_COLLIS - bool "-> Collis" - -config BOARD_GOOGLE_VOLET - bool "-> Volet" - -config BOARD_GOOGLE_CHRONICLER - bool "-> Chronicler" -- To view, visit https://review.coreboot.org/c/coreboot/+/74853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Gerrit-Change-Number: 74853 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/volteer: Add VBT data files for variants
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74852 ) Change subject: mb/google/volteer: Add VBT data files for variants ...................................................................... mb/google/volteer: Add VBT data files for variants Add data.vbt files for all variants supported by current volteer recovery image. Several boards use the same VBT, so place the "common" VBT under the baseboard directory and set it as the default. For variants with a unique VBT, override the default and use the file in their respective variant directory. Select INTEL_GMA_HAVE_VBT for all variants which have a VBT file. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/volteer/Kconfig A src/mainboard/google/volteer/variants/baseboard/data.vbt A src/mainboard/google/volteer/variants/elemi/data.vbt A src/mainboard/google/volteer/variants/voema/data.vbt 4 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 51210e4..c4d6f4a 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -41,9 +41,11 @@ config BOARD_GOOGLE_DELBIN select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_ELDRID select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_HALVOR select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -82,6 +84,7 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVER_I2C_TPM_ACPI select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select VARIANT_HAS_MIPI_CAMERA @@ -95,32 +98,40 @@ config BOARD_GOOGLE_VOXEL select BOARD_GOOGLE_BASEBOARD_VOLTEER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_ELEMI select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_VOEMA select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT select VARIANT_HAS_MIPI_CAMERA config BOARD_GOOGLE_DROBIT select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_COPANO select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_COLLIS select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_VOLET select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_CHRONICLER select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -165,6 +176,11 @@ hex default 0x50 +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(VARIANT_DIR)/data.vbt" \ + if BOARD_GOOGLE_ELEMI || BOARD_GOOGLE_LINDAR || BOARD_GOOGLE_VOEMA + default "src/mainboard/\$(MAINBOARDDIR)/variants/baseboard/data.vbt" if INTEL_GMA_HAVE_VBT + config MAINBOARD_DIR default "google/volteer" diff --git a/src/mainboard/google/volteer/variants/baseboard/data.vbt b/src/mainboard/google/volteer/variants/baseboard/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/elemi/data.vbt b/src/mainboard/google/volteer/variants/elemi/data.vbt new file mode 100644 index 0000000..f3597e2 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/voema/data.vbt b/src/mainboard/google/volteer/variants/voema/data.vbt new file mode 100644 index 0000000..6242c7fd --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/74852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Gerrit-Change-Number: 74852 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/adl: Unhide PMC, IOM ACPI devices from OS
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74850 ) Change subject: soc/intel/adl: Unhide PMC, IOM ACPI devices from OS ...................................................................... soc/intel/adl: Unhide PMC, IOM ACPI devices from OS These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/banshee, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: CoolStar <coolstarorganization(a)gmail.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/alderlake/pmc.c 2 files changed, 24 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified CoolStar: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 5c95997..6f8edda 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -331,8 +331,7 @@ Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - /* Hide the device so that Windows does not complain on missing driver */ - Name (_STA, 0xB) + Name (_STA, 0xF) } /* diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index c28ee2d..c9a089b 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -108,8 +108,7 @@ acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); - /* Hide the device so that Windows does not complain on missing driver */ - acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). -- To view, visit https://review.coreboot.org/c/coreboot/+/74850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae Gerrit-Change-Number: 74850 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/tgl: Unhide PMC, IOM ACPI devices from OS
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74829 ) Change subject: soc/intel/tgl: Unhide PMC, IOM ACPI devices from OS ...................................................................... soc/intel/tgl: Unhide PMC, IOM ACPI devices from OS These were hidden because no Windows drivers existed, but now that they do, the ACPI devices need to be visible in order for the drivers to properly attach. TEST=build google/drobit, boot Windows, verify Windows drivers correctly attach to PCM/IOM devices. Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: CoolStar <coolstarorganization(a)gmail.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/tigerlake/pmc.c 2 files changed, 23 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified CoolStar: Looks good to me, but someone else must approve Sean Rhodes: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 98337a3..5af78ed 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -331,8 +331,7 @@ Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - /* Hide the device so that Windows does not complain on missing driver */ - Name (_STA, 0xB) + Name (_STA, 0xF) } /* diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 5ad8a89..51d46f8 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -107,8 +107,7 @@ acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); - /* Hide the device so that Windows does not complain on missing driver */ - acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). -- To view, visit https://review.coreboot.org/c/coreboot/+/74829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983 Gerrit-Change-Number: 74829 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/jasperlake: Enable early caching of RAMTOP region
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74518 ) Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74518/comment/f70f1fd7_ceb3e553 PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of : 16MB) same Q as with CML, how does this affect boards with a 32MB flash? -- To view, visit https://review.coreboot.org/c/coreboot/+/74518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Gerrit-Change-Number: 74518 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 01 May 2023 14:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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