coreboot-gerrit May 2023

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[S] Change in coreboot[master]: soc/intel/jasperlake: Enable early caching of RAMTOP region
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74518 ) Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74518/comment/f70f1fd7_ceb3e553 PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of : 16MB) same Q as with CML, how does this affect boards with a 32MB flash? -- To view, visit https://review.coreboot.org/c/coreboot/+/74518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216 Gerrit-Change-Number: 74518 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 01 May 2023 14:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cometlake: Enable early caching of RAMTOP region
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74517 ) Change subject: soc/intel/cometlake: Enable early caching of RAMTOP region ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74517/comment/c4ce3649_42c2895b PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of : 16MB) how does this affect CML boards with a 32MB flash? There's a handful of google/hatch and puff variants which use 32MB flash -- To view, visit https://review.coreboot.org/c/coreboot/+/74517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75 Gerrit-Change-Number: 74517 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 01 May 2023 14:44:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoney/acpi: Unhide PCI0 root device from OS
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74855 ) Change subject: soc/amd/stoney/acpi: Unhide PCI0 root device from OS ...................................................................... soc/amd/stoney/acpi: Unhide PCI0 root device from OS In order for Windows to detect/load drivers for any child devices, the PCI0 root device status must be enabled and visible. TEST=build google/liara, boot Windows, verify PCI child devices visible in Device Manager. Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/acpi/northbridge.asl 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 7ed6225..c47b7b7 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -15,7 +15,7 @@ Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0F) /* Status is visible */ } Method(_PRT,0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/74855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Gerrit-Change-Number: 74855 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74796 ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync ...................................................................... soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 25 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 73cb51bc..1eb3eff 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -256,9 +256,8 @@ config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE bool default n - depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW help - Use this option for CSE FW Update when compressed blobs are used. + Use this option if CSE RW update needs to be triggered during RAMSTAGE. config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT bool -- To view, visit https://review.coreboot.org/c/coreboot/+/74796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Gerrit-Change-Number: 74796 Gerrit-PatchSet: 10 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: acpi: Add missing cbfs_unmap()
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74715 ) Change subject: acpi: Add missing cbfs_unmap() ...................................................................... acpi: Add missing cbfs_unmap() cbfs_map() can allocate memory, so cbfs_unmap() should be called before leaving the function. BUG=b:278264488 TEST=Built and run with additional debugs on Skyrim device to confirm that data are correctly unmapped Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Signed-off-by: Grzegorz Bernacki <bernacki(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74715 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-by: Tim Van Patten <timvp(a)google.com> --- M src/acpi/acpi.c 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, but someone else must approve Tim Van Patten: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index a57d498..10b0707 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1905,6 +1905,7 @@ || dsdt_file->length < sizeof(acpi_header_t) || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); + cbfs_unmap(dsdt_file); return current; } @@ -1914,6 +1915,7 @@ || slic_file->length < sizeof(acpi_header_t) || (memcmp(slic_file->signature, "SLIC", 4) != 0 && memcmp(slic_file->signature, "MSDM", 4) != 0))) { + cbfs_unmap(slic_file); slic_file = 0; } @@ -1998,8 +2000,17 @@ current += slic_file->length; current = acpi_align_current(current); acpi_add_table(rsdp, slic); + cbfs_unmap(slic_file); } + /* + * cbfs_unmap() uses mem_pool_free() which works correctly only + * if freeing is done in reverse order than memory allocation. + * This is why unmapping of dsdt_file must be done after + * unmapping slic file. + */ + cbfs_unmap(dsdt_file); + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); ssdt = (acpi_header_t *)current; acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); -- To view, visit https://review.coreboot.org/c/coreboot/+/74715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ba6842f42404ad8bb415f8e7fda10403cbe2e Gerrit-Change-Number: 74715 Gerrit-PatchSet: 6 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: avoid camera LED blinking during boot
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74728 ) Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot ...................................................................... mb/google/nissa/var/craask: avoid camera LED blinking during boot Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:274634319 TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior. Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7 Signed-off-by: Jimmy Su <jimmy.su(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 37 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Jimmy Su: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index e65ac80..6bc1635 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -397,6 +397,8 @@ register "remote_name" = ""IPU0"" register "has_power_resource" = "1" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + #Controls register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" @@ -431,6 +433,7 @@ register "chip_name" = ""Ov 8856 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" register "has_power_resource" = "1" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "ssdb.lanes_used" = "2" register "ssdb.link_used" = "1" @@ -474,8 +477,20 @@ register "chip_name" = ""DW AF DAC"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "has_power_resource" = "1" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 0C on probe WFC WFC_MIPI_OVTI5675 @@ -489,8 +504,6 @@ register "chip_name" = ""GT24C08"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/74728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7 Gerrit-Change-Number: 74728 Gerrit-PatchSet: 3 Gerrit-Owner: Jimmy Su <jimmy.su(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jimmy Su <jimmy.su(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Yeh <andy.yeh(a)intel.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: Tian Shu Qiu <tian.shu.qiu(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74801 ) Change subject: mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin ...................................................................... mb/siemens/mc_ehl: Remove wrong comment regarding spd.bin The support for a spd.bin from CBFS was removed for all mc_ehl boards in commit 833bb448c5213 (mb/siemens/mc_ehl: Remove spd.bin from CBFS). There is still a remaining comment in romstage_fsp_params.c referring to the removed capability. This fix removes the spd.bin related part of the comment to stay consistent with the code. Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801 Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved Jan Samek: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 506bcc6..98c9348 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -17,8 +17,7 @@ static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE]; const char *cbfs_hwi_name = "hwinfo.hex"; - /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to - spd.bin in the case where the SPD data in HW-Info is not available or invalid. */ + /* Initialize SPD information for LPDDR4x from HW-Info. */ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && -- To view, visit https://review.coreboot.org/c/coreboot/+/74801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14 Gerrit-Change-Number: 74801 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: vendorcode/mediatek/mt8192: Cast enum types
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74546 ) Change subject: vendorcode/mediatek/mt8192: Cast enum types ...................................................................... vendorcode/mediatek/mt8192: Cast enum types Clang warns about using the wrong enum types as arguments. Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74546 Reviewed-by: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c 1 file changed, 23 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Xixi Chen: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c index 4a98d8d..e267154 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c @@ -153,6 +153,7 @@ unsigned int vio18, vcore, vdram, vddq, vmddr; vio18 = vcore = vdram = vddq = vmddr = 0; + (void)vio18; #if __ETT__ hqa_set_voltage_by_freq(p, &vio18, &vcore, &vdram, &vddq, &vmddr); @@ -1502,11 +1503,11 @@ #endif #if ((!defined(FIRST_BRING_UP)) || (ENABLE_DRAM_SINGLE_FREQ_SELECT != 0xFF)) && (!__FLASH_TOOL_DA__) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, p->pDFSTable->shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)p->pDFSTable->shuffleIdx); #if SUPPORT_SAVE_TIME_FOR_CALIBRATION DramcSave_Time_For_Cal_End(p); #endif - LoadShuffleSRAMtoDramc(p, p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) + LoadShuffleSRAMtoDramc(p, (DRAM_DFS_SHUFFLE_TYPE_T)p->pDFSTable->shuffleIdx, DRAM_DFS_SHUFFLE_2); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) #if ENABLE_SRAM_DMA_WA DPHYSRAMShuWAToSHU1(p); //Darren: DDR1600 for MRW (DramcModeRegInit_LP4 and CBT) #endif @@ -1534,7 +1535,7 @@ // ignore the calibration for shuffle which is not in allCaliShuIdx, just copy first cali shuffle data if (!(allCaliShuIdx & BIT(u1ShuIdx))) { // copy first calibration shuffle to this shuffle (if DVFS, need double confirm) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx].shuffleIdx); continue; } @@ -1554,10 +1555,10 @@ RunTime_Shmoo_update_parameters(p); } #endif - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx].shuffleIdx); + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx].shuffleIdx); #if (fcFOR_CHIP_ID == fcMargaux) && (ENABLE_DRAM_SINGLE_FREQ_SELECT == 0xFF) // @Darren, new chip need double confirm if ((p->DRAMPinmux == PINMUX_DSC) && (gFreqTbl[u1ShuIdx].shuffleIdx == SRAM_SHU1)) - DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, gFreqTbl[u1ShuIdx + 1].shuffleIdx); // Copy SRAM_SHU1 to SRAM_SHU0 + DramcSaveToShuffleSRAM(p, DRAM_DFS_SHUFFLE_1, (DRAM_DFS_SHUFFLE_TYPE_T)gFreqTbl[u1ShuIdx + 1].shuffleIdx); // Copy SRAM_SHU1 to SRAM_SHU0 #endif #if SUPPORT_SAVE_TIME_FOR_CALIBRATION @@ -2699,4 +2700,3 @@ #endif //SW_CHANGE_FOR_SIMULATION #endif // __A60868_TO_BE_PORTING__ ///TODO: wait for porting --- - -- To view, visit https://review.coreboot.org/c/coreboot/+/74546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Gerrit-Change-Number: 74546 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V
by Tim Wawrzynczak (Code Review) 01 May '23

01 May '23

Attention is currently required from: Philipp Hug, weidongwd, ron minnich. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74799 ) Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V ...................................................................... Patch Set 1: (2 comments) File src/Kconfig: https://review.coreboot.org/c/coreboot/+/74799/comment/31d2bbbf_defc8450 PS1, Line 859: #depends on ARCH_X86 `depends on ARCH_X86 || ARCH_RISCV` ? File src/arch/riscv/smbios.c: PS1: Much of this looks common to x86 & RISC-V, seems like it would be simpler to have a common file and two architecture-specific ones? -- To view, visit https://review.coreboot.org/c/coreboot/+/74799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c47d22e8e383e8c90387caab82796b6b4d5eff5 Gerrit-Change-Number: 74799 Gerrit-PatchSet: 1 Gerrit-Owner: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 01 May 2023 14:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V
by Tim Wawrzynczak (Code Review) 01 May '23

01 May '23

Attention is currently required from: Philipp Hug, weidongwd, ron minnich. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74799 ) Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Is this based on https://github.com/riscv-non-isa/riscv-acpi ? I think it would make sense to move any x86-specific stuff to a new file, maybe `acpi_x86.c` or similar and try to make this file as architecture-agnostic as possible, which it mostly already is. -- To view, visit https://review.coreboot.org/c/coreboot/+/74799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c47d22e8e383e8c90387caab82796b6b4d5eff5 Gerrit-Change-Number: 74799 Gerrit-PatchSet: 1 Gerrit-Owner: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: weidongwd <weidong.wd(a)bytedance.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 01 May 2023 14:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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