coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/myst: Inject SPD binaries to APCB
by Karthik Ramasubramanian (Code Review) 01 May '23

01 May '23

Attention is currently required from: Jon Murphy, Martin Roth, Tim Van Patten. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74746 ) Change subject: mb/google/myst: Inject SPD binaries to APCB ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/myst/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74746/comment/7f73dbaf_7a7860b2 PS1, Line 18: APCB_PHX_D5 > APCB so far is known/expected to be compatible between Phoenix and its refresh SoCs. […] Marking it as resolved for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/74746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Gerrit-Change-Number: 74746 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Comment-Date: Mon, 01 May 2023 17:36:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: protectcli/vault_bsw: Drop USB power control bits in GNVS
by Kyösti Mälkki (Code Review) 01 May '23

01 May '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74859 ) Change subject: protectcli/vault_bsw: Drop USB power control bits in GNVS ...................................................................... protectcli/vault_bsw: Drop USB power control bits in GNVS There is no platform-level implementation for USB port power management in various sleepstates. This mainboard never evaluates the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers. Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74859 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/protectli/vault_bsw/acpi_tables.c 1 file changed, 18 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index 4206cde..4276be7 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -1,15 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <acpi/acpi_gnvs.h> -#include <soc/acpi.h> -#include <soc/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; -} +#include <acpi/acpi.h> void mainboard_fill_fadt(acpi_fadt_t *fadt) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c Gerrit-Change-Number: 74859 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mainboard/*: Drop USB power control bits in GNVS
by Kyösti Mälkki (Code Review) 01 May '23

01 May '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74858 ) Change subject: mainboard/*: Drop USB power control bits in GNVS ...................................................................... mainboard/*: Drop USB power control bits in GNVS There is no platform-level implementation for USB port power management in various sleepstates. The mainboards changed here never evaluate the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI handlers. Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> --- M src/mainboard/apple/macbookair4_2/gnvs.c M src/mainboard/bostentech/gbyt4/acpi_tables.c M src/mainboard/facebook/fbg1701/acpi_tables.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/dcp847ske/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/portwell/m107/acpi_tables.c 9 files changed, 20 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Frans Hendriks: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 5ec2f712..8ba9667 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -5,14 +5,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* the lid is open by default. */ gnvs->lids = 1; diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c index dc0d7a2..d53e97c 100644 --- a/src/mainboard/bostentech/gbyt4/acpi_tables.c +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* TPM not present */ gnvs->tpmp = 0; diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 3576455..d5dc5cc 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 33f4b6b..83e3165 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -8,14 +8,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* TPM Present */ gnvs->tpmp = 1; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 189f7f4..bc8ce27 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -9,12 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 927f7bc..675f732 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -9,17 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - /* TPM Present */ gnvs->tpmp = 1; diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index b8d4421..64f3f04 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -6,14 +6,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 by default */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Enable USB ports in S5 by default */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index c6d4ce8..d24238d 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -9,12 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 3576455..d5dc5cc 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/74858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Gerrit-Change-Number: 74858 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: SMBIOS: Group Kconfig dependency
by Kyösti Mälkki (Code Review) 01 May '23

01 May '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74451 ) Change subject: SMBIOS: Group Kconfig dependency ...................................................................... SMBIOS: Group Kconfig dependency Change-Id: I5a75a7230fd78c0a9926adc491059f55647cc9a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74451 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/Kconfig 1 file changed, 19 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 9042719..50381ae 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -889,10 +889,11 @@ bool default n +if GENERATE_SMBIOS_TABLES + config MAINBOARD_SERIAL_NUMBER prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO string - depends on GENERATE_SMBIOS_TABLES default "123456789" help The Serial Number to store in SMBIOS structures. @@ -900,7 +901,6 @@ config MAINBOARD_VERSION prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO string - depends on GENERATE_SMBIOS_TABLES default "1.0" help The Version Number to store in SMBIOS structures. @@ -908,7 +908,6 @@ config MAINBOARD_SMBIOS_MANUFACTURER prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO string - depends on GENERATE_SMBIOS_TABLES default MAINBOARD_VENDOR help Override the default Manufacturer stored in SMBIOS structures. @@ -916,7 +915,6 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO string - depends on GENERATE_SMBIOS_TABLES default MAINBOARD_PART_NUMBER help Override the default Product name stored in SMBIOS structures. @@ -924,13 +922,15 @@ config VPD_SMBIOS_VERSION bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'" default n - depends on VPD && GENERATE_SMBIOS_TABLES + depends on VPD help Selecting this option will read firmware_version from VPD_RO and override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. +endif + endmenu source "payloads/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/74451 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a75a7230fd78c0a9926adc491059f55647cc9a3 Gerrit-Change-Number: 74451 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/intel/microcode: Implement microcode info caching inside cbmem
by build bot (Jenkins) (Code Review) 01 May '23

01 May '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74873 ) Change subject: cpu/intel/microcode: Implement microcode info caching inside cbmem ...................................................................... Patch Set 2: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175300): https://review.coreboot.org/c/coreboot/+/74873/comment/41cd0206_b894f6d4 PS2, Line 6: Possible long commit subject (prefer a maximum 65 characters) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175300): https://review.coreboot.org/c/coreboot/+/74873/comment/1fc8b3ca_b5b9b4b2 PS2, Line 34: microcode: Update skipped, already up-to-date Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Gerrit-Change-Number: 74873 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 May 2023 17:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/microcode: Implement microcode info caching inside cbmem
by Subrata Banik (Code Review) 01 May '23

01 May '23

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74873 ) Change subject: cpu/intel/microcode: Implement microcode info caching inside cbmem ...................................................................... cpu/intel/microcode: Implement microcode info caching inside cbmem This patch implements microcode info caching inside cbmem (during ramstage) to avoid boot time penalty. Currently, locating ucode from cbfs is a continuous process in every boot hence, there are boot time penalties knowing typically `cpu_microcode_blob.bin` is consists of multiple microcodes as per different CPU steppings. Adding more microcode into `cpu_microcode_blob.bin` would increase the boot time cost. Hence, this patch enables caching of microcode related information inside cbmem that can be used to avoid microcode searching time during the warm resets. Additionally, use a tab to align `CBMEM_ID_CSE_PARTITION_VERSION` with other CBMEM ID macros. TEST=Build and boot google/rex with this patch which saves 11ms of boot time. Without this patch during warm reset: cbmem -c | grep microcode CBFS: Found 'cpu_microcode_blob.bin' @0x1e180 size 0x35400 in mcache @0x76add080 microcode: sig=0x906a4 pf=0x80 revision=0x423 microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date boot time: 954:calling FspSiliconInit 788,614 (5,414) 955:returning from FspSiliconInit 823,803 (35,188) With this patch during warm reset: cbmem -c | grep microcode microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date boot time: 954:calling FspSiliconInit 786,475 (5,390) 955:returning from FspSiliconInit 811,083 (24,608) Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/cpu/intel/microcode/microcode.c M src/include/cpu/intel/microcode.h 3 files changed, 99 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74873/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Gerrit-Change-Number: 74873 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: doc/tutorial/part1.md: fix package name to install qemu on Debian
by Nico Huber (Code Review) 01 May '23

01 May '23

Attention is currently required from: Daniel Rosa Franzini. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74894 ) Change subject: doc/tutorial/part1.md: fix package name to install qemu on Debian ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74894/comment/3007fd8a_895431cc PS1, Line 7: Documentation/tutorial/part1.md > This prefix doesn't have to be a full path. It only should point into […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibae9031a3e397925db95b7283fa8c6573f6d5858 Gerrit-Change-Number: 74894 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Daniel Rosa Franzini <danielt3(a)usp.br> Gerrit-Comment-Date: Mon, 01 May 2023 16:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
by Martin L Roth (Code Review) 01 May '23

01 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Kyösti Mälkki, Fred Reitberger, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74839 ) Change subject: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Gerrit-Change-Number: 74839 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 16:30:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report HPET MMIO
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74847 ) Change subject: soc/amd/common/block/lpc/lpc: report HPET MMIO ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77471d464dddffc63bb2f005fef3a33c84ff5f5e Gerrit-Change-Number: 74847 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 16:24:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report eSPI MMIO
by Matt DeVillier (Code Review) 01 May '23

01 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74845 ) Change subject: soc/amd/common/block/lpc/lpc: report eSPI MMIO ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63fb70da3e9ded6c05354f94ee69bc6dd04e58f0 Gerrit-Change-Number: 74845 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 16:23:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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