coreboot-gerrit May 2023

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[S] Change in coreboot[master]: src/mb/googe/rex/variants/rex0_ISH/overridetree: Enable ISH
by Jay Patel (Code Review) 01 May '23

01 May '23

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[S] Change in coreboot[master]: src/mb/google/rex/variants/rex0_ISH/gpio: config ISH GPIO
by Jay Patel (Code Review) 01 May '23

01 May '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Jay Patel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74876 ) Change subject: src/mb/google/rex/variants/rex0_ISH/gpio: config ISH GPIO ...................................................................... src/mb/google/rex/variants/rex0_ISH/gpio: config ISH GPIO Add ISH entries to GPIO table. BUG= TEST=None Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: I5869ba9ef404c3a7fef45af990dee14a3980ca3f --- M src/mainboard/google/rex/variants/rex0_ISH/gpio.c 1 file changed, 29 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/74876/1 diff --git a/src/mainboard/google/rex/variants/rex0_ISH/gpio.c b/src/mainboard/google/rex/variants/rex0_ISH/gpio.c index 71e9959..9fd8375 100644 --- a/src/mainboard/google/rex/variants/rex0_ISH/gpio.c +++ b/src/mainboard/google/rex/variants/rex0_ISH/gpio.c @@ -49,10 +49,10 @@ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_B01 : [] ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_B01, 1, DEEP), - /* GPP_B02 : net NC is not present in the given design */ - PAD_NC(GPP_B02, NONE), - /* GPP_B03 : net NC is not present in the given design */ - PAD_NC(GPP_B03, NONE), + /* GPP_B02 : ISH i2c0_SDA, net NC is not present in the given design */ + PAD_CFG_NF(GPP_B02, NONE, DEEP, NF3), + /* GPP_B03 : ISH_i2c0_SCL, net NC is not present in the given design */ + PAD_CFG_NF(GPP_B03, NONE, DEEP, NF3), /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ PAD_NC(GPP_B04, NONE), /* GPP_B05 : [] ==> SPKR_INT_L_R */ @@ -61,8 +61,8 @@ PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), /* GPP_B07 : [] ==> RST_HP_L */ PAD_CFG_GPO(GPP_B07, 1, DEEP), - /* GPP_B08 : net NC is not present in the given design */ - PAD_NC(GPP_B08, NONE), + /* GPP_B08 : ISH_GP3, net NC is not present in the given design */ + PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), /* GPP_B09 : [] ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPP_B10 : [] ==> WIFI_DISABLE_L */ @@ -151,10 +151,10 @@ PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), /* GPP_D04 : [] ==> EN_SPKR */ PAD_CFG_GPO(GPP_D04, 1, DEEP), - /* GPP_D05 : net NC. Test pad. */ - PAD_NC(GPP_D05, NONE), - /* GPP_D06 : net NC. Test pad.*/ - PAD_NC(GPP_D06, NONE), + /* GPP_D05 : ISH_UART_TX, net NC. Test pad. */ + PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), + /* GPP_D06 : ISH_UART_RX, net NC. Test pad.*/ + PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL */ PAD_CFG_GPO_LOCK(GPP_D07, 1, LOCK_CONFIG), /* GPP_D08 : net NC. Test pad. */ @@ -220,8 +220,8 @@ PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), - /* GPP_E15 : net NC is not present in the given design */ - PAD_NC(GPP_E15, NONE), + /* GPP_E15 : ISH_GP5A, net NC is not present in the given design */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF8), /* GPP_E16 : net NC. Test pad. */ PAD_NC(GPP_E16, NONE), /* GPP_E17 : [] ==> EN_HPS_PWR */ @@ -273,8 +273,8 @@ PAD_NC(GPP_F20, NONE), /* GPP_F21 : [] ==> GPP_F21_STRAP */ PAD_NC(GPP_F21, NONE), - /* GPP_F22 : net NC is not present in the given design */ - PAD_NC(GPP_F22, NONE), + /* GPP_F22 : ISH_GP8A, net NC is not present in the given design */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF8), /* GPP_F23 : net NC is not present in the given design */ PAD_NC(GPP_F23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/74876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5869ba9ef404c3a7fef45af990dee14a3980ca3f Gerrit-Change-Number: 74876 Gerrit-PatchSet: 1 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: src/mb/google/rex/variants: Add directory for new variant rex0_ISH
by Jay Patel (Code Review) 01 May '23

01 May '23

Jay Patel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74875 ) Change subject: src/mb/google/rex/variants: Add directory for new variant rex0_ISH ...................................................................... src/mb/google/rex/variants: Add directory for new variant rex0_ISH This commit adds a directory for rex0 based variant which includes Integrated Sensor Hub. This directory is a copy of rex0 variant directory. BUG= TEST=None Signed-off-by: Jay Patel <jay2.patel(a)intel.com> Change-Id: Ib94aae318822a29746678d6636f732045c2ff9b1 --- A src/mainboard/google/rex/variants/rex0_ISH/Makefile.inc A src/mainboard/google/rex/variants/rex0_ISH/fw_config.c A src/mainboard/google/rex/variants/rex0_ISH/gpio.c A src/mainboard/google/rex/variants/rex0_ISH/include/variant/ec.h A src/mainboard/google/rex/variants/rex0_ISH/include/variant/gpio.h A src/mainboard/google/rex/variants/rex0_ISH/memory/Makefile.inc A src/mainboard/google/rex/variants/rex0_ISH/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/rex0_ISH/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb A src/mainboard/google/rex/variants/rex0_ISH/variant.c 10 files changed, 1,349 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74875/1 diff --git a/src/mainboard/google/rex/variants/rex0_ISH/Makefile.inc b/src/mainboard/google/rex/variants/rex0_ISH/Makefile.inc new file mode 100644 index 0000000..cdbf407 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/rex/variants/rex0_ISH/fw_config.c b/src/mainboard/google/rex/variants/rex0_ISH/fw_config.c new file mode 100644 index 0000000..7d7c901 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/fw_config.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> + +#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a)) + +static const struct pad_config dmic_disable_pads[] = { + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), +}; + +static const struct pad_config sndw_disable_pads[] = { + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), +}; + +static const struct pad_config i2s_disable_pads[] = { + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, DN_20K), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { + printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98363_CS42L42_SNDW))) { + printk(BIOS_INFO, "Configure GPIOs for SoundWire audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + } +} diff --git a/src/mainboard/google/rex/variants/rex0_ISH/gpio.c b/src/mainboard/google/rex/variants/rex0_ISH/gpio.c new file mode 100644 index 0000000..71e9959 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/gpio.c @@ -0,0 +1,443 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: 3EC4CE58201758F4 + * Overrides: c826ba419f06f9df9cded8e60633253ddc7b60ff + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <console/console.h> +#include <boardid.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + /* GPP_A11 : [] ==> EN_UCAM_SENR_PWR */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 : [] ==> EN_UCAM_PWR */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* GPP_A13 : [] ==> SD_PE_LS_PRSNT_L */ + PAD_CFG_GPI_LOCK(GPP_A13, NONE, LOCK_CONFIG), + /* GPP_A14 : [] ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A14, 1, DEEP), + /* GPP_A15 : [] ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), + /* GPP_A16 : GPP_A16 ==> ESPI_SOC_ALERT_L configured on reset, do not touch */ + /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), + + /* GPP_A18 : [] ==> CAM_PSW_L */ + PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG), + /* GPP_A21 : [] ==> WWAN_CONFIG2 */ + PAD_CFG_GPI(GPP_A21, NONE, DEEP), + + /* GPP_B00 : [] ==> TCHPAD_INT_ODL_LS */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B00, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_B01 : [] ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_B01, 1, DEEP), + /* GPP_B02 : net NC is not present in the given design */ + PAD_NC(GPP_B02, NONE), + /* GPP_B03 : net NC is not present in the given design */ + PAD_NC(GPP_B03, NONE), + /* GPP_B04 : GPP_B04_STRAP ==> Component NC */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05 : [] ==> SPKR_INT_L_R */ + PAD_CFG_GPI(GPP_B05, NONE, DEEP), + /* GPP_B06 : [] ==> HP_INT_L_R */ + PAD_CFG_GPI_INT(GPP_B06, NONE, PLTRST, EDGE_BOTH), + /* GPP_B07 : [] ==> RST_HP_L */ + PAD_CFG_GPO(GPP_B07, 1, DEEP), + /* GPP_B08 : net NC is not present in the given design */ + PAD_NC(GPP_B08, NONE), + /* GPP_B09 : [] ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 : [] ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_B10, 1, DEEP), + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_B11, 1, LOCK_CONFIG), + /* GPP_B12 : [] ==> SLP_SO_R_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 : [] ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 : GPP_B14_STRAP ==> Component NC */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15 : [] ==> USB_OC3# */ + PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), + /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* GPP_B17 : [] ==> EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), + /* GPP_B20 : [] ==> SOC_I2C_MISC_SDA */ + PAD_CFG_NF_LOCK(GPP_B20, NONE, NF2, LOCK_CONFIG), + /* GPP_B21 : [] ==> SOC_I2C_MISC_SCL */ + PAD_CFG_NF_LOCK(GPP_B21, NONE, NF2, LOCK_CONFIG), + /* GPP_B22 : [] ==> USB4_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 : [] ==> WWAN_CONFIG0 */ + PAD_CFG_GPI_LOCK(GPP_B23, NONE, LOCK_CONFIG), + + /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ + PAD_CFG_GPO(GPP_C00, 0, DEEP), + /* GPP_C01 : [] ==> SOC_TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_C01, 0, DEEP), + /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03 : [] ==> EN_WCAM_SENR_PWR */ + PAD_CFG_GPO_LOCK(GPP_C03, 0, LOCK_CONFIG), + /* GPP_C04 : [] ==> EN_WCAM_PWR */ + PAD_CFG_GPO_LOCK(GPP_C04, 0, LOCK_CONFIG), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */ + PAD_CFG_GPO(GPP_C05, 1, PLTRST), + /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */ + PAD_CFG_GPO(GPP_C06, 0, DEEP), + /* GPP_C07 : [] ==> SOC_TCHSCR_INT */ + PAD_CFG_GPI_APIC(GPP_C07, NONE, PLTRST, LEVEL, NONE), + /* GPP_C08 : [] ==> SOCHOT_ODL */ + PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), + /* GPP_C09 : net NC is not present in the given design */ + PAD_NC(GPP_C09, NONE), + /* GPP_C10 : net NC is not present in the given design */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 : [] ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 : [] ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13 : [] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C15 : [] ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* GPP_C16 : [] ==> USB_C0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 : [] ==> USB_C0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 : [] ==> USB_C0_AUX_DC_P */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF6), + /* GPP_C19 : [] ==> USB_C0_AUX_DC_N */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF6), + /* GPP_C20 : [] ==> USB_C1_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21 : [] ==> USB_C1_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22 : [] ==> SOC_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_C22, 0, LOCK_CONFIG), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_C23, 1, LOCK_CONFIG), + + /* GPP_D00 : WCAM_MCLK_R */ + PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), + /* GPP_D01 : [] ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI_LOCK(GPP_D01, NONE, LOCK_CONFIG), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO_LOCK(GPP_D03, 1, LOCK_CONFIG), + /* GPP_D04 : [] ==> EN_SPKR */ + PAD_CFG_GPO(GPP_D04, 1, DEEP), + /* GPP_D05 : net NC. Test pad. */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06 : net NC. Test pad.*/ + PAD_NC(GPP_D06, NONE), + /* GPP_D07 : [] ==> FPMCU_UWB_MUX_SEL */ + PAD_CFG_GPO_LOCK(GPP_D07, 1, LOCK_CONFIG), + /* GPP_D08 : net NC. Test pad. */ + PAD_NC(GPP_D08, NONE), + /* GPP_D09 : [] ==> I2S_MCLK_R */ + PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2), + /* GPP_D10 : [] ==> I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11 : [] ==> I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12 : [] ==> I2S_SOC_TX_SPKR_RX_R_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF2), + /* GPP_D13 : [] ==> I2S_SOC_RX_SPKR_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* GPP_D14 : [] ==> I2S_HP_SCLK_R */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF2), + /* GPP_D15 : [] ==> I2S_HP_SFRM_R */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF2), + /* GPP_D16 : [] ==> I2S_SOC_TX_HP_RX_R */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2), + /* GPP_D17 : [] ==> I2S_SOC_RX_HP_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* GPP_D18 : net NC is not present in the given design */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 : net NC is not present in the given design */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20 : net NC is not present in the given design */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21 : [] ==> WLAN_CLKREQ_ODLl */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 : net NC is not present in the given design */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 : net NC is not present in the given design */ + PAD_NC(GPP_D23, NONE), + + /* GPP_E00 : [] ==> SAR1_INT_L */ + PAD_CFG_GPI_APIC(GPP_E00, NONE, PLTRST, LEVEL, NONE), + /* GPP_E01 : MEM_STRAP_2 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), + /* GPP_E02 : MEM_STRAP_1 ==> Component NC */ + PAD_CFG_GPI_LOCK(GPP_E02, NONE, LOCK_CONFIG), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E03, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E04 : [] ==> HPS_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E04, NONE, PLTRST, LEVEL, NONE), + /* GPP_E05 : [] ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E05, 1, DEEP), + /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07 : [] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_E08 : [] ==> SAR2_INT_L */ + PAD_CFG_GPI_APIC_LOCK(GPP_E08, NONE, LEVEL, NONE, LOCK_CONFIG), + /* GPP_E09 : No heuristic was found useful */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), + /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E10, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E11 : [] ==> MEM_STRAP_0 */ + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* GPP_E12 : [] ==> MEM_STRAP_3 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* GPP_E14 : [] ==> SOC_EDP_HPD_L */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 : net NC is not present in the given design */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16 : net NC. Test pad. */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17 : [] ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* GPP_E22 : [] ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), + + /* GPP_F00 : [] ==> CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 : [] ==> CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 : [] ==> CNV_RGI_DT_Rl */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 : [] ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 : [] ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 : [] ==> CNV_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 : [] ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07 : [] ==> UCAM_MCLK_R */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + /* GPP_F08 : [] ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F08, 1, DEEP), + /* GPP_F09 : [] ==> WLAN_PE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F09, NONE, PLTRST, LEVEL, INVERT), + /* GPP_F10 : [] ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F10, NONE, PLTRST, LEVEL, INVERT), + /* GPP_F11 : GSP1_SOC_CLK_R */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF5), + /* GPP_F12 : GSPI1_SOC_DO_FPMCU_DI_R */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF5), + /* GPP_F13 : GSPI1_SOC_DI_FPMCU_DO_LS */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF5), + /* GPP_F14 : GSPI0_SOC_DO_TCHSCR_DI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15 : [] ==> GSPI0_SOC_DI_TCHSCR_DO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16 : [] ==> GSPI0_SOC_TCHSCR_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F17 : [] ==> GSPI1_SOC_CS_L */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), + /* GPP_F18 : [] ==> GSPI0_SOC_TCHSCR_CS_L */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), + /* GPP_F19 : [] ==> GPP_F19_STRAP */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 : [] ==> GPP_F20_STRAP */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 : [] ==> GPP_F21_STRAP */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 : net NC is not present in the given design */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 : net NC is not present in the given design */ + PAD_NC(GPP_F23, NONE), + + /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H04 : [] ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), + /* GPP_H05 : [] ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), + /* GPP_H06 : [] ==> SOC_I2C_TCHPAD_SDA */ + PAD_CFG_NF_LOCK(GPP_H06, NONE, NF1, LOCK_CONFIG), + /* GPP_H07 : [] ==> SOC_I2C_TCHPAD_SCL */ + PAD_CFG_NF_LOCK(GPP_H07, NONE, NF1, LOCK_CONFIG), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), + /* GPP_H11 : net NC is not present in the given design */ + PAD_NC(GPP_H11, NONE), + /* GPP_H13 : [] ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : [] ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* GPP_H15 : [] ==> EN_DMIC_SOC_DATA */ + PAD_CFG_GPO(GPP_H15, 0, PLTRST), + /* GPP_H16 : [] ==> DDIB_HDMI_CTRLCLK*/ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* GPP_H17 : [] ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H19 : [] ==> SOC_I2C_AUD_WFC_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 : [] ==> SOC_I2C_AUD_WFC_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 : [] ==> SOC_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 : [] ==> SOC_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00 : [] ==> SDW_HP_CLK */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01 : [] ==> SDW_HP_DATA */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02 : [] ==> DMIC_SOC_CLK0_DB_RC */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF3), + /* GPP_S03 : [] ==> DMIC_SOC_DATA0_DB_R */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF3), + /* GPP_S04 : [] ==> SDW_SPKR_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF1), + /* GPP_S05 : [] ==> SDW_SPKR_DATA */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF1), + /* GPP_S06 : [] ==> DMIC_SOC_CLK1_DB_RC */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3), + /* GPP_S07 : [] ==> DMIC_SOC_DATA1_DB */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3), + + /* GPP_V00 : [] ==> BATLOW_L */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01 : [] ==> ACPRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02 : [] ==> EC_SOC_WAKE_ODL */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03 : [] ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04 : [] ==> SLP_S3_L */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 : [] ==> SLP_S4_L */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 : [] ==> SOC_SLP_A_L */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V08 : [] ==> SOC_SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 : [] ==> SOC_SLP_WLAN_L */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 : [] ==> SLP_S5_L */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 : [] ==> SOC_GPP_V11 testpoint*/ + PAD_NC(GPP_V11, NONE), + /* GPP_V12 : [] ==> SOC_SLP_LAN_L */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V14 : [] ==> SOC_WAKE_L */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V22 : [] ==> WCAM_RST_L */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + /* GPP_V23 : [] ==> UCAM_RST_L */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B17 : [] ==> EN_WWAN_PWR */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), + /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF2), + /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF2), + /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP (updated in ramstage) */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_A15 : [] ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + /* GPP_E03 : [] ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT), + + /* GPP_E07 : [] ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* GPP_D03 : [] ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D03, 1, DEEP), + + /* GPP_E13 : [] ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_H10 : [] ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + /* GPP_E07 : [] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_E07, 1, DEEP), + /* GPP_D02 : [] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/rex/variants/rex0_ISH/include/variant/ec.h b/src/mainboard/google/rex/variants/rex0_ISH/include/variant/ec.h new file mode 100644 index 0000000..4fc0622 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/rex/variants/rex0_ISH/include/variant/gpio.h b/src/mainboard/google/rex/variants/rex0_ISH/include/variant/gpio.h new file mode 100644 index 0000000..41c3798 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +/* TODO: Add GPIO as per rex board */ + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/rex/variants/rex0_ISH/memory/Makefile.inc b/src/mainboard/google/rex/variants/rex0_ISH/memory/Makefile.inc new file mode 100644 index 0000000..ee6d6e8 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/memory/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/rex0/memory src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/rex/variants/rex0_ISH/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/rex0_ISH/memory/dram_id.generated.txt new file mode 100644 index 0000000..47da118 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/rex0/memory src/mainboard/google/rex/variants/rex0/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D2DS-026 WT:B 1 (0001) +MT62F2G32D4DS-026 WT:B 2 (0010) +H58G56BK7BX068 1 (0001) +K3KL6L60GM-MGCT 3 (0011) diff --git a/src/mainboard/google/rex/variants/rex0_ISH/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/rex0_ISH/memory/mem_parts_used.txt new file mode 100644 index 0000000..c952558 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/memory/mem_parts_used.txt @@ -0,0 +1,16 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F512M32D2DR-031 WT:B +MT62F1G32D2DS-026 WT:B +MT62F2G32D4DS-026 WT:B +H58G56BK7BX068 +K3KL6L60GM-MGCT diff --git a/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb b/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb new file mode 100644 index 0000000..ef517df --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb @@ -0,0 +1,748 @@ +fw_config + field AUDIO 0 3 + option AUDIO_UNKNOWN 0 + option MAX98360_ALC5682I_I2S 1 + option MAX98363_CS42L42_SNDW 2 + end + field CELLULAR 4 5 + option CELLULAR_ABSENT 0 + option CELLULAR_USB 1 + option CELLULAR_PCIE 2 + end + field UFC 6 7 + option UFC_USB 0 + option UFC_MIPI 1 + end + field WFC 8 9 + option WFC_USB 0 + option WFC_MIPI 1 + end + field DB_SD 10 11 + option SD_ABSENT 0 + option SD_GL9755S 1 + end + field DB_USB 12 14 + option USB_UNKNOWN 0 + option USB3_PS8815 1 + option USB4_KB8010 2 + option USB4_ANX7452 3 + option USB4_HAYDEN_BRIDGE 4 + option USB4_ANX7452_V2 5 + end + field FP 15 + option FP_PRESENT 0 + option FP_ABSENT 1 + end + field UWB 16 17 + option UWB_ABSENT 0 + option UWB_BITBANG 1 + option UWB_GSPI1 2 + end + field WIFI 18 + option WIFI_CNVI 0 + option WIFI_PCIE 1 + end +end + +chip soc/intel/meteorlake + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Enable eDP in Port A + register "ddi_port_A_config" = "1" + # Enable HDMI in Port B + register "ddi_port_B_config" = "0" + + # Enable Display Port Configuration + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD, + [DDI_PORT_4] = DDI_ENABLE_HPD, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio and WFC | + #| I2C1 | Touchscreen | + #| I2C3 | Touchpad | + #| I2C4 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C5 | UFC, SAR1, SAR2, HPS | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[4] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 900, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""wwan"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 57000, + .max_power = 57000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie_rp9 on + # Enable SSD Card PCIE 9 using clk 4 + register "pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe CELLULAR CELLULAR_USB + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B09)" + device ref usb2_port6 on + probe UFC UFC_USB + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe CELLULAR CELLULAR_USB + end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on + probe WIFI WIFI_CNVI + end + end + end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used + register "cio2_lane_endpoint[0]" = ""^I2C0.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" + register "cio2_prt[0]" = "4" + register "cio2_prt[1]" = "0" + + device generic 0 on + probe UFC UFC_MIPI + probe WFC WFC_MIPI + end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_B06)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO MAX98360_ALC5682I_I2S + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTIDB10"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 13b10 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "4" + register "ssdb.link_used" = "0" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "560 * MHz" # 560 MHz + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" # FREQ_19_2_MHZ + + register "gpio_panel.gpio[0].gpio_num" = "GPP_C03" #EN_WCAM_SENR_PWR + register "gpio_panel.gpio[1].gpio_num" = "GPP_C04" #EN_WCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_V22" #WCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 0)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 10)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on + probe WFC WFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "2" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW9714 VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "vcm_compat" = ""dongwoon,dw9714"" + + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "1" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C04" #EN_WCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 0C on + probe WFC WFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "1" + register "acpi_name" = ""NVM0"" + register "chip_name" = ""ST M24C64X"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "nvm_compat" = ""atmel,24c64"" + + register "nvm_size" = "0x10000" + register "nvm_pagesize" = "0x01" + register "nvm_readonly" = "0x01" + register "nvm_width" = "0x0E" + + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "1" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C04" #EN_WCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 50 on + probe WFC WFC_MIPI + end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN6918"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c2 on end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B00_IRQ)" + register "wake" = "GPE0_DW0_00" + register "detect" = "1" + device i2c 15 on end + end + end + device ref i2c4 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" + device i2c 50 on end + end + end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3537"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Hi-556 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "437 * MHz" + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_A11" #EN_UCAM_SENR_PWR + register "gpio_panel.gpio[1].gpio_num" = "GPP_B09" #EN_FCAM_PWR + register "gpio_panel.gpio[2].gpio_num" = "GPP_V23" #UCAM_RST_L + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 20 on + probe UFC UFC_MIPI + end + end + chip drivers/intel/mipi_camera + register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" + register "acpi_uid" = "1" + register "acpi_name" = ""NVM1"" + register "chip_name" = ""ST M24C64X"" + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + + register "nvm_size" = "0x10000" + register "nvm_pagesize" = "1" + register "nvm_readonly" = "1" + register "nvm_width" = "0x10" + register "nvm_compat" = ""atmel,24c64"" + + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "1" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_B09" #EN_FCAM_PWR + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 50 on + probe UFC UFC_MIPI + end + end + end #I2C5 + device ref pcie_rp5 on + probe WIFI WIFI_PCIE + # Enable WLAN Card PCIE 5 using clk 5 + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)" + register "srcclk_pin" = "5" + device generic 0 on + probe WIFI WIFI_PCIE + end + end + end #PCIE5 WLAN card + device ref pcie_rp6 on + probe CELLULAR CELLULAR_PCIE + # Enable WWAN Card PCIE 6 using clk 3 + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "3" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on + probe CELLULAR CELLULAR_PCIE + end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E07)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A15)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C05)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" + register "add_acpi_dma_property" = "true" + use rp6_rtd3 as rtd3dev + device generic 0 alias rp6_wwan on + probe CELLULAR CELLULAR_PCIE + end + end + end #PCIE6 WWAN card + device ref pcie_rp7 on + # Enable SD Card PCIE 7 using clk 2 + register "pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D03)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "2" + device generic 0 on end + end + probe DB_SD SD_GL9755S + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)" + register "wake" = "GPE0_DW1_10" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "enable_delay_ms" = "3" + device spi 0 on end + end # FPMCU + end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D04)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98360_ALC5682I_I2S + end + end + end + end +end diff --git a/src/mainboard/google/rex/variants/rex0_ISH/variant.c b/src/mainboard/google/rex/variants/rex0_ISH/variant.c new file mode 100644 index 0000000..3aec24b --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0_ISH/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <fw_config.h> +#include <sar.h> +#include <variant/gpio.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) { + if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) + acpigen_soc_clear_tx_gpio(GPP_B09); + } else if (entry == S0IX_EXIT) { + if (fw_config_probe(FW_CONFIG(UFC, UFC_USB))) + acpigen_soc_set_tx_gpio(GPP_B09); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94aae318822a29746678d6636f732045c2ff9b1 Gerrit-Change-Number: 74875 Gerrit-PatchSet: 1 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/hp: Add new port for compaq_8300_elite_usdt
by Riku Viitanen (Code Review) 01 May '23

01 May '23

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74906 ) Change subject: mb/hp: Add new port for compaq_8300_elite_usdt ...................................................................... mb/hp: Add new port for compaq_8300_elite_usdt New port based on autoport. This board has NPCD379 SuperIO, which seems similar to NPCD378. So I added the SuperIO code from hp8200sff. Seems to work fine. Fan speeds stay low when idling. (Before, they went 100%) The following is tested and is working: * Native raminit with both DIMMs * Libgfxinit textmode and framebuffer on both DisplayPorts and VGA * External USB2 and USB3 ports: they all work * USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports) * Ethernet * Mini-PCIe WLAN * SATA: 2.5" SSD and optical drive bay * Booting Parabola GNU/Linux with SeaBIOS 1.16.1 * PS/2 keyboard * S3 suspend and resume, wake using USB keyboard * Headphone output, line out, internal speaker * Wake on LAN Untested: * mSATA slot. The SATA port needs to be enabled on devicetree too, but I'm unable to test due to lack of hardware * Line in, mic input * MXM graphics card * PS/2 mouse * EHCI debug Not working: * Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so maybe it just isn't present * PS/2 keyboard wake from S3 Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A Documentation/mainboard/hp/compaq_8300_usdt.md A Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg A src/mainboard/hp/compaq_8300_elite_usdt/Kconfig A src/mainboard/hp/compaq_8300_elite_usdt/Kconfig.name A src/mainboard/hp/compaq_8300_elite_usdt/Makefile.inc A src/mainboard/hp/compaq_8300_elite_usdt/acpi/ec.asl A src/mainboard/hp/compaq_8300_elite_usdt/acpi/platform.asl A src/mainboard/hp/compaq_8300_elite_usdt/acpi/superio.asl A src/mainboard/hp/compaq_8300_elite_usdt/acpi_tables.c A src/mainboard/hp/compaq_8300_elite_usdt/board_info.txt A src/mainboard/hp/compaq_8300_elite_usdt/devicetree.cb A src/mainboard/hp/compaq_8300_elite_usdt/dsdt.asl A src/mainboard/hp/compaq_8300_elite_usdt/early_init.c A src/mainboard/hp/compaq_8300_elite_usdt/gma-mainboard.ads A src/mainboard/hp/compaq_8300_elite_usdt/gpio.c A src/mainboard/hp/compaq_8300_elite_usdt/hda_verb.c A src/mainboard/hp/compaq_8300_elite_usdt/mainboard.c 17 files changed, 710 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74906/1 diff --git a/Documentation/mainboard/hp/compaq_8300_usdt.md b/Documentation/mainboard/hp/compaq_8300_usdt.md new file mode 100644 index 0000000..1d4a0c7 --- /dev/null +++ b/Documentation/mainboard/hp/compaq_8300_usdt.md @@ -0,0 +1,66 @@ +# HP Compaq 8300 Elite USDT + +This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop +from [HP]. + +## Flashing coreboot + +```eval_rst ++---------------------+-------------+ +| Type | Value | ++=====================+=============+ +| Socketed flash | no | ++---------------------+-------------+ +| Model | W25Q128BVFG | ++---------------------+-------------+ +| Size | 16 MiB | ++---------------------+-------------+ +| In circuit flashing | yes | ++---------------------+-------------+ +| Package | SOIC-16 | ++---------------------+-------------+ +| Write protection | No | ++---------------------+-------------+ +| Dual BIOS feature | No | ++---------------------+-------------+ +``` + +### Internal programming + +TODO: investigate + +The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?). + +### External programming + +Remove the lid. The flash chip can be found on the edge opposite to the CPU. +There is a spot for a "ROM RCVRY" header next to the flash chip but it is +unpopulated. If you don't feel like using a clip, you can easily solder +a standard pin header there yourself and use it for programming. + +Programming powers some parts of the board. Programming when +Wake on LAN is active works great. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | NPCD379HAKFX | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +### SuperIO + +This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work +fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`. + +[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/523… +[HP]: https://www.hp.com/ diff --git a/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg b/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg new file mode 100644 index 0000000..967f91c --- /dev/null +++ b/Documentation/mainboard/hp/compaq_8300_usdt_rom_header.jpg Binary files differ diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig b/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig new file mode 100644 index 0000000..a1784b6 --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig @@ -0,0 +1,39 @@ +if BOARD_HP_COMPAQ_8300_ELITE_USDT + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NPCD378 + select MAINBOARD_USES_IFD_GBE_REGION + +config CBFS_SIZE + default 0x570000 + +config MAINBOARD_DIR + string + default "hp/compaq_8300_elite_usdt" + +config MAINBOARD_PART_NUMBER + string + default "HP Compaq 8300 Elite USDT" + +config VGA_BIOS_ID + string + default "8086,0152" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig.name b/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig.name new file mode 100644 index 0000000..04cc409 --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_COMPAQ_8300_ELITE_USDT + bool "Compaq 8300 Elite USDT" diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/Makefile.inc b/src/mainboard/hp/compaq_8300_elite_usdt/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/acpi/ec.asl b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/ec.asl new file mode 100644 index 0000000..73fa78e --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/acpi/platform.asl b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/acpi/superio.asl b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/superio.asl new file mode 100644 index 0000000..54f8e3f --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/acpi/superio.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */ + +#include <superio/nuvoton/npcd378/acpi/superio.asl> + +Scope (\_GPE) +{ + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + //FIXME: Add GBE device + //Notify (\_SB.PCI0.GBE, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + } +} diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/acpi_tables.c b/src/mainboard/hp/compaq_8300_elite_usdt/acpi_tables.c new file mode 100644 index 0000000..8f4f83b --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/acpi_tables.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/board_info.txt b/src/mainboard/hp/compaq_8300_elite_usdt/board_info.txt new file mode 100644 index 0000000..0baebcc --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM protocol: SPI +ROM socketed: n +ROM package: SOIC-16 +Flashrom support: n +Release year: 2012 diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/devicetree.cb b/src/mainboard/hp/compaq_8300_elite_usdt/devicetree.cb new file mode 100644 index 0000000..c89b32b --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/devicetree.cb @@ -0,0 +1,169 @@ +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "0" + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc0801" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" # 0x1: 2.5" slot + # 0x2: DVD + # 0x?: mSATA + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device ref xhci on # USB 3.0 Controller + subsystemid 0x103c 0x3398 + end + device ref mei1 off # Management Engine Interface 1 + end + device ref mei2 off # Management Engine Interface 2 + end + device ref me_ide_r off # Management Engine IDE-R + end + device ref me_kt off # Management Engine KT + end + device ref gbe on # Intel Gigabit Ethernet + subsystemid 0x103c 0x3398 + end + device ref ehci2 on # USB2 EHCI #2 + subsystemid 0x103c 0x3398 + end + device ref hda on # High Definition Audio + subsystemid 0x103c 0x3398 + end + device ref pcie_rp1 on # Mini-PCIe WLAN + end + device ref pcie_rp2 off # PCIe Port #2 + end + device ref pcie_rp3 off # PCIe Port #3 + end + device ref pcie_rp4 off # PCIe Port #4 + end + device ref pcie_rp5 off # PCIe Port #5 + end + device ref pcie_rp6 off # PCIe Port #6 + end + device ref pcie_rp7 off # PCIe Port #7 + end + device ref pcie_rp8 off # PCIe Port #8 + end + device ref ehci1 on # USB2 EHCI #1 + subsystemid 0x103c 0x3398 + end + device ref pci_bridge on # PCI bridge + subsystemid 0x103c 0x3398 + end + device ref lpc on # LPC bridge + chip superio/common # Super I/O grabbed from 8200SFF devicetree + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x620 + end + device pnp 2e.8 on # HWM + io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector + + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 + + drq 0xf4 = 0x66 + drq 0xf5 = 0x67 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x08 + drq 0xfe = 0x80 + end + device pnp 2e.15 on # BUS ? + io 0x60 = 0x0680 + io 0x62 = 0x0690 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e on # GPIO ? + io 0x60 = 0x660 + drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end + end + end + end + device ref sata1 on # SATA Controller 1 + subsystemid 0x103c 0x3398 + end + device ref smbus on # SMBus + subsystemid 0x103c 0x3398 + end + device ref sata2 off # SATA Controller 2 + end + device ref thermal off # Thermal + end + end + device ref host_bridge on # Host bridge Host bridge + subsystemid 0x103c 0x3398 + end + device ref peg10 on # PEG + end + device ref igd on # iGPU + subsystemid 0x103c 0x3398 + end + end +end diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/dsdt.asl b/src/mainboard/hp/compaq_8300_elite_usdt/dsdt.asl new file mode 100644 index 0000000..7d13c55 --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/early_init.c b/src/mainboard/hp/compaq_8300_elite_usdt/early_init.c new file mode 100644 index 0000000..857c25d --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/early_init.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <superio/nuvoton/npcd378/npcd378.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[3], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); +} diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/gma-mainboard.ads b/src/mainboard/hp/compaq_8300_elite_usdt/gma-mainboard.ads new file mode 100644 index 0000000..74b5064 --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/gpio.c b/src/mainboard/hp/compaq_8300_elite_usdt/gpio.c new file mode 100644 index 0000000..2ae852a --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/hda_verb.c b/src/mainboard/hp/compaq_8300_elite_usdt/hda_verb.c new file mode 100644 index 0000000..9c0525b --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c3398, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c3398), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/compaq_8300_elite_usdt/mainboard.c b/src/mainboard/hp/compaq_8300_elite_usdt/mainboard.c new file mode 100644 index 0000000..8dbd95e --- /dev/null +++ b/src/mainboard/hp/compaq_8300_elite_usdt/mainboard.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/74906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Gerrit-Change-Number: 74906 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO
by Nick Vaccaro (Code Review) 01 May '23

01 May '23

Attention is currently required from: Tarun Tuli, Cliff Huang. Hello build bot (Jenkins), Cliff Huang, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74842 to look at the new patch set (#4). Change subject: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO ...................................................................... mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO Use the new PAD_CFG_OD() macro to configure the GPP_D1 gpio for the open-drain FP_RST_ODL signal for both brya0 and skolas. BUG=b:278732600 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot skolas to kernel, sleep and wake device and use fingerprint for wake authentication. Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/skolas/gpio.c 4 files changed, 40 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/74842/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Gerrit-Change-Number: 74842 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Angel Pons (Code Review) 01 May '23

01 May '23

Attention is currently required from: Sean Rhodes, Benjamin Doron, Christian Walter, Maximilian Brune, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74122 ) Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... Patch Set 3: (4 comments) File src/mainboard/prodrive/atlas/cfr.c: https://review.coreboot.org/c/coreboot/+/74122/comment/64aca694_d4e27d00 PS2, Line 123: .ui_helptext = "Specify what to do when power is re-applied " : "after a power loss. This option has no effect " : "on systems without a RTC battery.", /* TODO: check */ : > The help text is correct, to my knowledge. […] Will try File src/mainboard/prodrive/atlas/cfr.c: https://review.coreboot.org/c/coreboot/+/74122/comment/fea72a0d_e8b0309b PS3, Line 77: .opt_name = "DONOTSTOREME_sn", /* TODO: Make optional? */ Name still needed so that the value can be read. https://review.coreboot.org/c/coreboot/+/74122/comment/ca703e39_8a112188 PS3, Line 79: .flags = CFR_OPTFLAG_READONLY, Add another flag to indicate an option is volatile. https://review.coreboot.org/c/coreboot/+/74122/comment/13d4729c_43e8d98c PS3, Line 92: .ui_name = "", /* Empty UI name */ Define new tag for text fields (i.e. "comments"), these do not have an underlying variable but they should still have an option ID for dependencies -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 01 May 2023 20:11:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Add default vBIOS ID and location
by Martin L Roth (Code Review) 01 May '23

01 May '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74905 ) Change subject: soc/amd/phoenix: Add default vBIOS ID and location ...................................................................... soc/amd/phoenix: Add default vBIOS ID and location Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90 --- M src/soc/amd/phoenix/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74905/1 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 6df8fe7..f1b9e63 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -247,6 +247,17 @@ help Maximum number of threads the platform can have. +config VGA_BIOS_ID + string + default "1002,15BF" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in graphics.c. + +config VGA_BIOS_FILE + string + default "3rdparty/amd_blobs/phoenix/Vbios.bin" + config CONSOLE_UART_BASE_ADDRESS depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex -- To view, visit https://review.coreboot.org/c/coreboot/+/74905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadc32f4dbf8bd48d8666a213d7b5f3ba42175a90 Gerrit-Change-Number: 74905 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Don't hardcode ramtop offset
by Sean Rhodes (Code Review) 01 May '23

01 May '23

Attention is currently required from: Nico Huber, Subrata Banik, Dinesh Gehlot, Lean Sheng Tan. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74511 ) Change subject: soc/intel/common: Don't hardcode ramtop offset ...................................................................... Patch Set 11: (1 comment) File src/soc/intel/common/basecode/ramtop/ramtop.c: https://review.coreboot.org/c/coreboot/+/74511/comment/53d0a925_637ea3d4 PS10, Line 19: */ > This still seems like valuable information. OTOH, we could also add a […] Runtime error? -- To view, visit https://review.coreboot.org/c/coreboot/+/74511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0 Gerrit-Change-Number: 74511 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 01 May 2023 19:58:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO
by Nick Vaccaro (Code Review) 01 May '23

01 May '23

Attention is currently required from: Tarun Tuli, Cliff Huang. Hello build bot (Jenkins), Cliff Huang, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74842 to look at the new patch set (#3). Change subject: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO ...................................................................... mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO Use the new PAD_CFG_OD() macro to configure the GPP_D1 gpio for the open-drain FP_RST_ODL signal. BUG=b:278732600 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot skolas to kernel, sleep and wake device and use fingerprint for wake authentication. Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya0/variant.c 3 files changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/74842/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Gerrit-Change-Number: 74842 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: src/mainboard/rex: Perform CSE FW update in RAMSTAGE
by Anil Kumar K (Code Review) 01 May '23

01 May '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74764 ) Change subject: src/mainboard/rex: Perform CSE FW update in RAMSTAGE ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/74764/comment/bd4f7791_14a32931 PS3, Line 42: select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE > please follow the order Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e59b0c61e852d5c3b7357292039211fcdbb0aa Gerrit-Change-Number: 74764 Gerrit-PatchSet: 7 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 01 May 2023 19:25:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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