coreboot-gerrit May 2023

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[S] Change in coreboot[master]: [Test] soc/intel/cse_lite: check PSR bit before issuing PSR backup co...
by Anil Kumar K (Code Review) 01 May '23

01 May '23

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74874 ) Change subject: [Test] soc/intel/cse_lite: check PSR bit before issuing PSR backup command ...................................................................... [Test] soc/intel/cse_lite: check PSR bit before issuing PSR backup command Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/74874/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1ad67ef..48dc04f 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -775,6 +775,19 @@ if (cse_boot_to_rw(cse_bp_info) == CB_SUCCESS) { + uint32_t feature_status; + /* first check if PSR is supported by the SKU */ + if (cse_get_fw_feature_state(&feature_status) != CB_SUCCESS) { + printk(BIOS_ERR, "cse_get_fw_feature_state command failed !\n"); + return; + } + + if (!(feature_status & ME_FW_FEATURE_PSR)) { + printk(BIOS_DEBUG, "PSR is not supported in this SKU !\n"); + /* PSR is not supported in this SKU */ + return; + } + static struct psr_heci_fw_downgrade_backup_res backup_psr_resp; if (cse_send_backup_psr_cmd(&backup_psr_resp) != CB_SUCCESS) { printk(BIOS_ERR, "backup_psr command failed ! PSR data is not backed up\n"); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 1eda029..be32027 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -34,6 +34,7 @@ /* Firmware Feature Shipment Time State Override Command Id */ #define MKHI_GEN_FW_FEATURE_SHIPMENT_OVER 0x14 #define ME_FW_FEATURE_PTT BIT(29) +#define ME_FW_FEATURE_PSR BIT(5) /* Get Firmware Feature State Command Id */ #define MKHI_FWCAPS_GET_FW_FEATURE_STATE 0x02 -- To view, visit https://review.coreboot.org/c/coreboot/+/74874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e92341a9dc799146eb8f1a70b3a4a16fd1aa0ae Gerrit-Change-Number: 74874 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74904 ) Change subject: mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I reworked this patch set to use cmos.default to configure the auto power on setting in the EC BRAM. cmos.default can now span both bank 0 and bank 1, and the I/O base addresses for both can be configured (so Librem Mini can use the EC BRAM bank 1 while continuing to use the PCH for bank 0). The only peculiarity is that I had to set up the EC BRAM bank 1 in bootblock now since cmos.default is applied in bootblock. This meant duplicating a bit of setup that the device tree would handle anyway, but it's not that much, and the cmos.default handling probably needs to stay in early bootblock for boards that actually have options used during boot (this one is not). -- To view, visit https://review.coreboot.org/c/coreboot/+/74904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808 Gerrit-Change-Number: 74904 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 May 2023 19:00:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Jonathon Hall has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74903 ) Change subject: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses ...................................................................... drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Librem Mini v1/v2 has an automatic power-on setting provided by the EC that can be configured in its BRAM bank 1. The RTC uses the PCH CMOS, and it is preferable not to change this in an update, as the RTC would reset. By configuring these addresses, we can use the PCH CMOS bank 0 and the EC BRAM bank 1. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/pc80/rtc/Kconfig M src/drivers/pc80/rtc/mc146818rtc.c M src/include/pc80/mc146818rtc.h 3 files changed, 43 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74903/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Gerrit-Change-Number: 74903 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74904 ) Change subject: mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1 ...................................................................... mb/purism/librem_cnl: Use EC BRAM bank 1 as CMOS memory bank 1 Librem Mini v1/v2 has an automatic power-on setting provided by the EC in BRAM bank 1. Use this bank as the high bank of CMOS memory so that setting can be described in cmos.layout. Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/74904/1 diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index f0fd6a8..45bbdc2 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -61,6 +61,13 @@ endif +if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 + +config PC_CMOS_BASE_PORT_BANK1 + default 0x360 + +endif + config ENABLE_EC_UART1 bool "Enable EC UART1" depends on BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808 Gerrit-Change-Number: 74904 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74903 ) Change subject: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses ...................................................................... drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Librem Mini v1/v2 has an automatic power-on setting provided by the EC that can be configured in its BRAM bank 1. The RTC uses the PCH CMOS, and it is preferable not to change this in an update, as the RTC would reset. By configuring these addresses, we can use the PCH CMOS bank 0 and the EC BRAM bank 1. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/pc80/rtc/Kconfig M src/drivers/pc80/rtc/mc146818rtc.c M src/include/pc80/mc146818rtc.h 3 files changed, 47 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74903/1 diff --git a/src/drivers/pc80/rtc/Kconfig b/src/drivers/pc80/rtc/Kconfig index 0d06457..7a1c398 100644 --- a/src/drivers/pc80/rtc/Kconfig +++ b/src/drivers/pc80/rtc/Kconfig @@ -9,3 +9,11 @@ depends on DRIVERS_MC146818 help May be useful for legacy OSes that assume its presence. + +config PC_CMOS_BASE_PORT_BANK0 + hex "Base port for CMOS bank 0 index/data registers" + default 0x70 + +config PC_CMOS_BASE_PORT_BANK1 + hex "Base port for CMOS bank 1 index/data registers" + default 0x72 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index f45a3a0..6474ecb 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -249,11 +249,11 @@ { uint8_t index, byte; - index = inb(RTC_PORT(0)) & 0x80; + index = inb(RTC_PORT_BANK0(0)) & 0x80; index |= RTC_BOOT_BYTE; - outb(index, RTC_PORT(0)); + outb(index, RTC_PORT_BANK0(0)); - byte = inb(RTC_PORT(1)); + byte = inb(RTC_PORT_BANK0(1)); if (CONFIG(SKIP_MAX_REBOOT_CNT_CLEAR)) { /* @@ -269,5 +269,5 @@ byte &= 0x0f; } - outb(byte, RTC_PORT(1)); + outb(byte, RTC_PORT_BANK0(1)); } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 383c41f..98ea965 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -5,10 +5,12 @@ #include <arch/io.h> #include <types.h> +#include <console/console.h> -#define RTC_BASE_PORT 0x70 +#define RTC_BASE_PORT_BANK0 (CONFIG_PC_CMOS_BASE_PORT_BANK0) +#define RTC_BASE_PORT_BANK1 (CONFIG_PC_CMOS_BASE_PORT_BANK1) -#define RTC_PORT(x) (RTC_BASE_PORT + (x)) +#define RTC_PORT_BANK0(x) (RTC_BASE_PORT_BANK0 + (x)) /* control registers - Moto names */ @@ -107,24 +109,27 @@ static inline unsigned char cmos_read(unsigned char addr) { - int offs = 0; + int port = RTC_BASE_PORT_BANK0; if (addr >= 128) { - offs = 2; + port = RTC_BASE_PORT_BANK1; addr -= 128; } - outb(addr, RTC_BASE_PORT + offs + 0); - return inb(RTC_BASE_PORT + offs + 1); + outb(addr, port + 0); + uint8_t val = inb(port + 1); + printk(BIOS_SPEW, "%s: addr %02X at base %02X -> val %02X\n", __func__, + addr, port, val); + return val; } static inline void cmos_write_inner(unsigned char val, unsigned char addr) { - int offs = 0; + int port = RTC_BASE_PORT_BANK0; if (addr >= 128) { - offs = 2; + port = RTC_BASE_PORT_BANK1; addr -= 128; } - outb(addr, RTC_BASE_PORT + offs + 0); - outb(val, RTC_BASE_PORT + offs + 1); + outb(addr, port + 0); + outb(val, port + 1); } static inline u8 cmos_disable_rtc(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/74903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Gerrit-Change-Number: 74903 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74902 ) Change subject: drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1 ...................................................................... drivers/pc80/rtc/option.c: Allow CMOS defaults to extend to bank 1 CMOS defaults greater than 128 bytes long will extend to bank 1. Change-Id: I9ee8364d01dd8520be101de3f83d2302d50c7283 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/pc80/rtc/option.c 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/74902/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index e8e2345..bb295cc 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -211,7 +211,8 @@ return; u8 control_state = cmos_disable_rtc(); - for (i = 14; i < MIN(128, length); i++) + /* Max length of 256 spans bank 0 and bank 1 */ + for (i = 14; i < MIN(256, length); i++) cmos_write_inner(cmos_default[i], i); cmos_restore_rtc(control_state); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee8364d01dd8520be101de3f83d2302d50c7283 Gerrit-Change-Number: 74902 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
by Jonathon Hall (Code Review) 01 May '23

01 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. Hello build bot (Jenkins), Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74363 to look at the new patch set (#4). Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ...................................................................... mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 Define a CMOS layout for Librem Mini v1/v2 spanning both banks. The only setting provided is the automatic power-on setting, which is implemented by the EC. This can now be configured in a firmware image by adding a cmos.default to CBFS. Since cmos.default is applied early in bootblock, the EC BRAM interface must now be configured in bootblock, including opening the LPC I/O range. Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig M src/mainboard/purism/librem_cnl/Kconfig.name M src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c A src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout 5 files changed, 79 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74363/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 01 May '23

01 May '23

Attention is currently required from: Subrata Banik. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 27: (2 comments) This change is ready for review. File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/74577/comment/2c618c1e_732c89e1 PS17, Line 84: #define PSR_BACKUP_STATUS_CMOS_OFFSET 161 > how do u know if this offset is not occupied by some other operation already ? i found this by adding prints in cmos_write to check the list of addresses being accessed. I am not aware if there is a better way to identify a free space https://review.coreboot.org/c/coreboot/+/74577/comment/11133242_2c61dfbb PS17, Line 114: typedef > don't use `typedef` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 27 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 01 May 2023 18:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO
by Nick Vaccaro (Code Review) 01 May '23

01 May '23

Attention is currently required from: Tarun Tuli, Cliff Huang. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74842 ) Change subject: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Gerrit-Change-Number: 74842 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Mon, 01 May 2023 18:45:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/gpio: Add open-drain GPIO macros
by Nick Vaccaro (Code Review) 01 May '23

01 May '23

Attention is currently required from: Cliff Huang, Julius Werner. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74841 ) Change subject: soc/intel/common/gpio: Add open-drain GPIO macros ...................................................................... Patch Set 2: (4 comments) File src/include/gpio.h: https://review.coreboot.org/c/coreboot/+/74841/comment/0b26c47d_5cb6fde8 PS1, Line 18: void gpio_set_HiZ(gpio_t gpio_num); > I don't really think these belong here in the platform-independent API as separate calls. […] Ack File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/74841/comment/ebc9b0a4_5378d7a3 PS1, Line 724: ~(PAD_CFG0_TX_STATE & PAD_CFG0_TX_DISABLE), > Since this change ensures that TX_DISBLE is not set when drive TX output, it can be added to gpio_se […] Ack File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/74841/comment/2f2c09f6_bfa2b2e9 PS1, Line 292: #define PAD_CFG_OD_GPO(pad, rst) \ > Since TX is disabled. […] Done https://review.coreboot.org/c/coreboot/+/74841/comment/9077382f_105d322c PS1, Line 299: #define PAD_CFG_OD_GPO_LOCK(pad, lock_action) \ > Since TX is disabled. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca9915c7574e741c20af2e8dc91f6a07f7c0d26 Gerrit-Change-Number: 74841 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 01 May 2023 18:43:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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