coreboot-gerrit April 2023

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Tim Van Patten (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 3: (3 comments) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/74736/comment/41462666_09aec6ca PS3, Line 1402: &chip_h[strlen("src/")] I don't understand this indexing into `chip_h`. Is the assumption that `mainboard_path` begins with (if so, why can we assume that?)? Or was this meant to find the substring "src/" first, and then starting `fprintf`'ing from there? https://review.coreboot.org/c/coreboot/+/74736/comment/d6281a98_b6483f55 PS3, Line 1405: free(mainboard_path); This is potentially a double-free, since `mainboard_path` does not always allocate its own memory (ref1). Instead, either an additional flag needs to indicate when the `free()` should be done, or `mainboard_path` needs to always have memory allocated for it, rather than reusing memory in some cases. https://review.coreboot.org/c/coreboot/+/74736/comment/108e4f24_285f99e9 PS3, Line 2030: mainboard_path = base_devtree_dir; ref1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:38:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO
by Nick Vaccaro (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Tarun Tuli. Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74842 ) Change subject: mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO ...................................................................... mb/google/brya: configure GPP_D1 using PAD_CFG_OD_GPO Use the new PAD_CFG_OD_GPO() macro to configure the GPP_D1 gpio for the open-drain FP_RST_ODL signal. BUG=b:278732600 BRANCH=firmware-brya-14505.B TEST='emerge-brya coreboot chromeos-bootimage', flash and boot skolas to kernel, sleep and wake device and use fingerprint for wake authentication. Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya0/variant.c 3 files changed, 36 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/74842/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index f3ab850..b73384e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -120,7 +120,7 @@ /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO_LOCK(GPP_D1, 0, LOCK_CONFIG), + PAD_CFG_OD_GPO_LOCK(GPP_D1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG), /* D3 : ISH_GP3 ==> WCAM_RST_L */ @@ -402,7 +402,7 @@ * later on in ramstage. Since reset signal is asserted in bootblock, it results in * FPMCU not working after a S3 resume. This is a known issue. */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_OD_GPO(GPP_D1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index f406f4b..55d7b26 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -49,7 +49,7 @@ * later on in ramstage. Since reset signal is asserted in bootblock, it results in * FPMCU not working after a S3 resume. This is a known issue. */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_OD_GPO(GPP_D1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ @@ -92,7 +92,7 @@ * later on in ramstage. Since reset signal is asserted in bootblock, it results in * FPMCU not working after a S3 resume. This is a known issue. */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_OD_GPO(GPP_D1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ @@ -138,7 +138,7 @@ * Since reset signal is asserted in bootblock, it results in FPMCU not * working after a S3 resume. This is a known issue. */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_OD_GPO(GPP_D1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ @@ -168,7 +168,7 @@ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_OD_GPO(GPP_D1, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 0, DEEP), diff --git a/src/mainboard/google/brya/variants/brya0/variant.c b/src/mainboard/google/brya/variants/brya0/variant.c index e9ae51e..0883740 100644 --- a/src/mainboard/google/brya/variants/brya0/variant.c +++ b/src/mainboard/google/brya/variants/brya0/variant.c @@ -1,11 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> #include <chip.h> #include <fw_config.h> -#include <baseboard/variants.h> +#include <gpio.h> void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) { config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW)); } + +void variant_init(void) +{ + /* + * Hold the FP MCU in reset. This is performed here as there's not a + * macro to initialize a value for an open-drain gpio. + */ + gpio_od_set(GPP_D1, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66ff974c6222e38a7584a756dba0e4714d1e5797 Gerrit-Change-Number: 74842 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common/gpio: Add open-drain GPIO macros
by Nick Vaccaro (Code Review) 28 Apr '23

28 Apr '23

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74841 ) Change subject: soc/intel/common/gpio: Add open-drain GPIO macros ...................................................................... soc/intel/common/gpio: Add open-drain GPIO macros Add PAD_CFG_OD_GPI, PAD_CFG_OD_GPI_LOCK, PAD_CFG_OD_GPO, and PAD_CFG_OD_GPO_LOCK macros to support open-drain signals. BUG=b:278732600 BRANCH=firmware-brya-14505.B TEST=None Change-Id: I8ca9915c7574e741c20af2e8dc91f6a07f7c0d26 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/include/gpio.h M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74841/1 diff --git a/src/include/gpio.h b/src/include/gpio.h index 9fe854b..c42b5b5 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -14,6 +14,8 @@ /* The following functions must be implemented by SoC/board code. */ int gpio_get(gpio_t gpio); +void gpio_od_set(gpio_t gpio, int value); +void gpio_set_HiZ(gpio_t gpio_num); int gpio_tx_get(gpio_t gpio); void gpio_set(gpio_t gpio, int value); void gpio_input_pulldown(gpio_t gpio); diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index facc1fe..ff3dfb5 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -713,6 +713,29 @@ return gpio_lock_pads(&pads, 1); } +/* gpio_od_set(): use for open-drain output gpios */ +void gpio_od_set(gpio_t gpio_num, int value) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + uint16_t config_offset; + + config_offset = pad_config_offset(comm, gpio_num); + pcr_rmw32(comm->port, config_offset, + ~(PAD_CFG0_TX_STATE & PAD_CFG0_TX_DISABLE), + (!!value & PAD_CFG0_TX_STATE)); +} + +/* gpio_od_set(): use for set an open-drain output gpio to hi-z */ +void gpio_set_HiZ(gpio_t gpio_num) +{ + const struct pad_community *comm = gpio_get_community(gpio_num); + uint16_t config_offset; + + config_offset = pad_config_offset(comm, gpio_num); + pcr_rmw32(comm->port, config_offset, + ~PAD_CFG0_TX_DISABLE, PAD_CFG0_TX_DISABLE); +} + void gpio_set(gpio_t gpio_num, int value) { const struct pad_community *comm = gpio_get_community(gpio_num); diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 654d6f2..83391b3 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -265,6 +265,44 @@ PAD_RESET(rst) | PAD_FUNC(func) | PAD_CFG0_NAFVWE_ENABLE,\ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) +/* + * General purpose input for open drain + * enable RX, no pullup/down + * during standby: Hi-Z, Rx driving 1 back to its controller internally + */ +#define PAD_CFG_OD_GPI(pad, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(NONE) | PAD_IOSSTATE(HIZCRx1)) + +/* + * General purpose input with lock for open drain + * enable RX, no pullup/down + * during standby: Hi-Z, Rx driving 1 back to its controller internally + */ +#define PAD_CFG_OD_GPI_LOCK(pad, lock_action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \ + PAD_PULL(NONE) | PAD_IOSSTATE(HIZCRx1), \ + PAD_LOCK(lock_action)) + +/* General purpose output for open drain, no pullup/down. */ +#define PAD_CFG_OD_GPO(pad, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ + PAD_PULL(NONE) | PAD_IOSSTATE(HIZCRx1)) + +/* General purpose output with lock for open drain, no pullup/down. */ +#define PAD_CFG_OD_GPO_LOCK(pad, lock_action) \ + _PAD_CFG_STRUCT_LOCK(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \ + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), \ + PAD_PULL(NONE) | PAD_IOSSTATE(HIZCRx1), \ + PAD_LOCK(lock_action)) + /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/74841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca9915c7574e741c20af2e8dc91f6a07f7c0d26 Gerrit-Change-Number: 74841 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by build bot (Jenkins) (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74840 ) Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... Patch Set 2: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175230): https://review.coreboot.org/c/coreboot/+/74840/comment/3e63fa76_cafe38f5 PS2, Line 19: PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags c0040100 index 10000000 Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175230): https://review.coreboot.org/c/coreboot/+/74840/comment/6a3b9ce2_b2caec5e PS2, Line 20: PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags c0040100 index 10000100 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 Gerrit-Change-Number: 74840 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:19:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74840 to look at the new patch set (#2). Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC The 2*4 IO ports from 0xcf8 to 0xcff are used for the IO-based PCI config space access, so they wont be decoded to the LPC device and the devices below it, so split the subtractive IO range of the LPC device that those IO ports aren't covered by the subtractive IO regions of the LPC device. TEST=The coreboot console output on mandolin now shows the two subtractive IO regions on the LPC device instead of the one that also covered the PCI config IO ports: PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags c0040100 index 10000000 PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags c0040100 index 10000100 The contents of /proc/mem are still identical. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74840/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 Gerrit-Change-Number: 74840 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74736/comment/addede07_11280c79 PS1, Line 9: Include > I thought about adding an option to update the name of the mainboard chip. […] Implemented Raul's suggestion. Commit Message: https://review.coreboot.org/c/coreboot/+/74736/comment/3df8c5c6_246a793e PS2, Line 8: > 'defintions' may be misspelled - perhaps 'definitions'? Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:14:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74809 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window ...................................................................... soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window This ports back commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/74809 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 19 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index dad8aaa..a4903e9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -98,16 +98,9 @@ CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = 0x10000000 << 4 + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0 -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74804 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ...................................................................... soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2e..dad8aaa 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -111,6 +111,11 @@ Local0 -= TOM1 MM1L = Local0 + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Gerrit-Change-Number: 74804 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held. Hello build bot (Jenkins), Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74736 to look at the new patch set (#3). Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... util/sconfig: Include optional maiboard chip header Mainboard chip headers can contain definitions that can be referenced in the devicetree. One of the potential use-cases is for the hardware configurations in devicetree to refer to net names instead of cryptic GPIO numbers. This helps to improve the code readability. Add support to include mainboard chip header, if present. BUG=None TEST=Build Skyrim BIOS with & without mainboard chip header. Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M util/sconfig/main.c 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74736/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by build bot (Jenkins) (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175229): https://review.coreboot.org/c/coreboot/+/74736/comment/62d42a7c_f4dac32a PS2, Line 8: 'defintions' may be misspelled - perhaps 'definitions'? -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:12:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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