coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/amd/common/block/cpu: Add missing cbfs_unmap()
by Tim Van Patten (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Konrad Adamczyk, Jason Glenesk, Raul Rangel, Jakub Czapiga, Matt DeVillier, Paul Menzel, Grzegorz Bernacki, Arthur Heymans, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74777 ) Change subject: soc/amd/common/block/cpu: Add missing cbfs_unmap() ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/74777/comment/99ede524_92b71690 PS3, Line 102: goto end; I don't think we need a `goto` here, and is hurting readability more than helping simplify the code. I prefer `cbfs_unmap()` with `return` instead, especially since it's branching into the middle of a conditional block. https://review.coreboot.org/c/coreboot/+/74777/comment/57bb888c_8aa3c208 PS3, Line 113: cbfs_unmap((void *)ucode); While the `>=` was added to make it more likely that this is called eventually, it also means it's possible for multiple CPUs to execute `cbfs_unmap()` at the same time, corrupting the CBFS cache data structures. There are a few things here: 1. This should be reverted back to `==`, so it's performed exactly once. 2. We should crash if we see `> get_cpu_count()`, since that indicates we've hit a (likely) fatal error. 3. The access to `ucode` needs to be within an semaphore that's incremented by every reader, so it's only freed once all current readers have completed. * The `== get_cpu_count()` will need to block until all readers are done, since it's the only one that can safely call `cbfs_unmap()`. * Otherwise, if the `> get_cpu_count()` case occurs, it's possible for CPUs to be loading microcode while the cache is being freed (and the memory potentially reused, meaning the microcode binary being loaded isn't actually microcode, but "random" data). * If we ignore the `> get_cpu_count()` case, then we can skip this step, since the atomic counter should be enough to prevent freeing the `ucode` memory until everyone is done with it. I'm not sure how possible `> get_cpu_count()` is, though. Ideally, we could catch that when releasing the other CPUs (before getting here?), but I don't know the details well enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/74777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I200d24df6157cc6d06bade34809faefea9f0090a Gerrit-Change-Number: 74777 Gerrit-PatchSet: 3 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 16:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Benjamin Doron (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Sean Rhodes, Christian Walter, Angel Pons, Maximilian Brune, Lean Sheng Tan. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74122 ) Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... Patch Set 2: (1 comment) File src/mainboard/prodrive/atlas/cfr.c: https://review.coreboot.org/c/coreboot/+/74122/comment/f2faf64e_f3f65c62 PS2, Line 123: .ui_helptext = "Specify what to do when power is re-applied " : "after a power loss. This option has no effect " : "on systems without a RTC battery.", /* TODO: check */ : The help text is correct, to my knowledge. The RTC power well is the deepest (as in, lowest power), without a battery the PMC cannot preserve volatile registers. Can we synchronise the default value with the Kconfig? Unfortunately, no actual Kconfig to use, so a ternary expression would do: `CONFIG(POWER_STATE_OFF_AFTER_FAILURE) ? MAINBOARD_POWER_STATE_OFF : MAINBOARD_POWER_STATE_ON` -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 16:01:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: device/allocator: Allow for multiple domain resources of a type
by Nico Huber (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jonathan Zhang, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67018 ) Change subject: device/allocator: Allow for multiple domain resources of a type ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67018/comment/7390f543_0c0206d9 PS6, Line 11: bridge devices Above it's domains, here bridge devices in general oO So far I don't understand why we should change something for all bridge resources and not only the domains. If it was only done to keep the code for domain and bridge resources aligned, CB:65420 tries to detangle them anyway (it used to be next in the relation chain right after the one we had to revert :-/). File src/device/resource_allocator_v4.c: https://review.coreboot.org/c/coreboot/+/67018/comment/3b140d4e_20e2164f PS6, Line 178: update_bridge_resource(bridge, res, type_match, print_depth); In there we'll filter child resources based on the type. If we had multiple bridge resources of the same type, we'd account for every child resource multiple times? -- To view, visit https://review.coreboot.org/c/coreboot/+/67018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a60c9a4438accdb06444e2b50cc9b0b2eb009 Gerrit-Change-Number: 67018 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 28 Apr 2023 15:58:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/volteer/Kconfig: Add variant model names
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Nick Vaccaro. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74854 ) Change subject: mb/google/volteer/Kconfig: Add variant model names ...................................................................... mb/google/volteer/Kconfig: Add variant model names Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/74854/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 9ee1bec..4d62a85 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,10 +1,10 @@ comment "Volteer" config BOARD_GOOGLE_CHRONICLER - bool "-> Chronicler" + bool "-> Chronicler (FMV Chromebook 14F)" config BOARD_GOOGLE_COLLIS - bool "-> Collis" + bool "-> Collis (Asus Chromebook Flip CX3)" config BOARD_GOOGLE_COPANO bool "-> Copano (ASUS Chromebook Flip CX5400)" @@ -16,7 +16,7 @@ bool "-> Drobit (ASUS Chromebook CX9400)" config BOARD_GOOGLE_ELDRID - bool "-> Eldrid" + bool "-> Eldrid (HP Chromebook x360 14c)" config BOARD_GOOGLE_ELEMI bool "-> Elemi (HP Pro c640 G2 Chromebook)" @@ -25,7 +25,7 @@ bool "-> Halvor" config BOARD_GOOGLE_LINDAR - bool "-> Lindar" + bool "-> Lindar (Lenovo 5i-14/Slim 5 Chromebook)" config BOARD_GOOGLE_MALEFOR bool "-> Malefor" @@ -40,10 +40,10 @@ bool "-> Trondo" config BOARD_GOOGLE_VOEMA - bool "-> Voema" + bool "-> Voema (Acer Chromebook Spin 514)" config BOARD_GOOGLE_VOLET - bool "-> Volet" + bool "-> Volet (Acer Chromebook 515)" config BOARD_GOOGLE_VOLTEER bool "-> Volteer" -- To view, visit https://review.coreboot.org/c/coreboot/+/74854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0 Gerrit-Change-Number: 74854 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Nick Vaccaro. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74853 ) Change subject: mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections ...................................................................... mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selections Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name 2 files changed, 79 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/74853/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index d73830f..57df6ce 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -27,26 +27,49 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS + select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50 select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS - select I2C_TPM if BOARD_GOOGLE_VOLTEER2_TI50 - select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_TIGERLAKE + select SPI_TPM if !BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_TI50 if BOARD_GOOGLE_VOLTEER2_TI50 select TPM_GOOGLE_CR50 if !BOARD_GOOGLE_VOLTEER2_TI50 +config BOARD_GOOGLE_CHRONICLER + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_COLLIS + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_COPANO + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_DELBIN select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_DROBIT + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + config BOARD_GOOGLE_ELDRID select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_ELEMI + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_HALVOR select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM @@ -74,6 +97,15 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM +config BOARD_GOOGLE_VOEMA + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + select VARIANT_HAS_MIPI_CAMERA + +config BOARD_GOOGLE_VOLET + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT + config BOARD_GOOGLE_VOLTEER select BOARD_GOOGLE_BASEBOARD_VOLTEER select INTEL_CAR_NEM @@ -101,38 +133,6 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES -config BOARD_GOOGLE_ELEMI - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_VOEMA - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - select VARIANT_HAS_MIPI_CAMERA - -config BOARD_GOOGLE_DROBIT - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select DRIVERS_GENESYSLOGIC_GL9755 - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_COPANO - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES - -config BOARD_GOOGLE_COLLIS - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_VOLET - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_CHRONICLER - select BOARD_GOOGLE_BASEBOARD_VOLTEER - select INTEL_GMA_HAVE_VBT - if BOARD_GOOGLE_BASEBOARD_VOLTEER config CHROMEOS @@ -184,50 +184,50 @@ default "Google_Volteer" config MAINBOARD_PART_NUMBER + default "Chronicler" if BOARD_GOOGLE_CHRONICLER + default "Collis" if BOARD_GOOGLE_COLLIS + default "Copano" if BOARD_GOOGLE_COPANO default "Delbin" if BOARD_GOOGLE_DELBIN + default "Drobit" if BOARD_GOOGLE_DROBIT default "Eldrid" if BOARD_GOOGLE_ELDRID + default "Elemi" if BOARD_GOOGLE_ELEMI default "Halvor" if BOARD_GOOGLE_HALVOR default "Lindar" if BOARD_GOOGLE_LINDAR default "Malefor" if BOARD_GOOGLE_MALEFOR default "Terrador" if BOARD_GOOGLE_TERRADOR default "Todor" if BOARD_GOOGLE_TODOR default "Trondo" if BOARD_GOOGLE_TRONDO + default "Voema" if BOARD_GOOGLE_VOEMA + default "Volet" if BOARD_GOOGLE_VOLET default "Volteer" if BOARD_GOOGLE_VOLTEER default "Volteer2" if BOARD_GOOGLE_VOLTEER2 default "Volteer2_Ti50" if BOARD_GOOGLE_VOLTEER2_TI50 default "Voxel" if BOARD_GOOGLE_VOXEL - default "Elemi" if BOARD_GOOGLE_ELEMI - default "Voema" if BOARD_GOOGLE_VOEMA - default "Drobit" if BOARD_GOOGLE_DROBIT - default "Copano" if BOARD_GOOGLE_COPANO - default "Collis" if BOARD_GOOGLE_COLLIS - default "Volet" if BOARD_GOOGLE_VOLET - default "Chronicler" if BOARD_GOOGLE_CHRONICLER config TPM_TIS_ACPI_INTERRUPT int default 21 # GPE0_DW0_21 (GPP_C21) config VARIANT_DIR + default "chronicler" if BOARD_GOOGLE_CHRONICLER + default "collis" if BOARD_GOOGLE_COLLIS + default "copano" if BOARD_GOOGLE_COPANO default "delbin" if BOARD_GOOGLE_DELBIN + default "drobit" if BOARD_GOOGLE_DROBIT default "eldrid" if BOARD_GOOGLE_ELDRID + default "elemi" if BOARD_GOOGLE_ELEMI default "halvor" if BOARD_GOOGLE_HALVOR default "lindar" if BOARD_GOOGLE_LINDAR default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR default "todor" if BOARD_GOOGLE_TODOR default "trondo" if BOARD_GOOGLE_TRONDO + default "voema" if BOARD_GOOGLE_VOEMA + default "volet" if BOARD_GOOGLE_VOLET default "volteer" if BOARD_GOOGLE_VOLTEER default "volteer2" if BOARD_GOOGLE_VOLTEER2 default "volteer2" if BOARD_GOOGLE_VOLTEER2_TI50 default "voxel" if BOARD_GOOGLE_VOXEL - default "elemi" if BOARD_GOOGLE_ELEMI - default "voema" if BOARD_GOOGLE_VOEMA - default "drobit" if BOARD_GOOGLE_DROBIT - default "copano" if BOARD_GOOGLE_COPANO - default "collis" if BOARD_GOOGLE_COLLIS - default "volet" if BOARD_GOOGLE_VOLET - default "chronicler" if BOARD_GOOGLE_CHRONICLER config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d868e52..9ee1bec 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -1,11 +1,26 @@ comment "Volteer" +config BOARD_GOOGLE_CHRONICLER + bool "-> Chronicler" + +config BOARD_GOOGLE_COLLIS + bool "-> Collis" + +config BOARD_GOOGLE_COPANO + bool "-> Copano (ASUS Chromebook Flip CX5400)" + config BOARD_GOOGLE_DELBIN bool "-> Delbin (ASUS Chromebook Flip CX5)" +config BOARD_GOOGLE_DROBIT + bool "-> Drobit (ASUS Chromebook CX9400)" + config BOARD_GOOGLE_ELDRID bool "-> Eldrid" +config BOARD_GOOGLE_ELEMI + bool "-> Elemi (HP Pro c640 G2 Chromebook)" + config BOARD_GOOGLE_HALVOR bool "-> Halvor" @@ -24,6 +39,12 @@ config BOARD_GOOGLE_TRONDO bool "-> Trondo" +config BOARD_GOOGLE_VOEMA + bool "-> Voema" + +config BOARD_GOOGLE_VOLET + bool "-> Volet" + config BOARD_GOOGLE_VOLTEER bool "-> Volteer" @@ -36,24 +57,3 @@ config BOARD_GOOGLE_VOXEL bool "-> Voxel (Acer Chromebook Spin 713 (CP713-3W))" - -config BOARD_GOOGLE_ELEMI - bool "-> Elemi (HP Pro c640 G2 Chromebook)" - -config BOARD_GOOGLE_VOEMA - bool "-> Voema" - -config BOARD_GOOGLE_DROBIT - bool "-> Drobit (ASUS Chromebook CX9400)" - -config BOARD_GOOGLE_COPANO - bool "-> Copano (ASUS Chromebook Flip CX5400)" - -config BOARD_GOOGLE_COLLIS - bool "-> Collis" - -config BOARD_GOOGLE_VOLET - bool "-> Volet" - -config BOARD_GOOGLE_CHRONICLER - bool "-> Chronicler" -- To view, visit https://review.coreboot.org/c/coreboot/+/74853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Gerrit-Change-Number: 74853 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/volteer: Add VBT data files for variants
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74852 ) Change subject: mb/google/volteer: Add VBT data files for variants ...................................................................... mb/google/volteer: Add VBT data files for variants Add data.vbt files for all variants supported by current volteer recovery image. Select INTEL_GMA_HAVE_VBT for those variants. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig A src/mainboard/google/volteer/variants/chronicler/data.vbt A src/mainboard/google/volteer/variants/collis/data.vbt A src/mainboard/google/volteer/variants/copano/data.vbt A src/mainboard/google/volteer/variants/delbin/data.vbt A src/mainboard/google/volteer/variants/drobit/data.vbt A src/mainboard/google/volteer/variants/eldrid/data.vbt A src/mainboard/google/volteer/variants/elemi/data.vbt A src/mainboard/google/volteer/variants/voema/data.vbt A src/mainboard/google/volteer/variants/volet/data.vbt A src/mainboard/google/volteer/variants/volteer2/data.vbt A src/mainboard/google/volteer/variants/voxel/data.vbt 12 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/74852/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 51210e4..d73830f 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -41,9 +41,11 @@ config BOARD_GOOGLE_DELBIN select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_ELDRID select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_HALVOR select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -82,6 +84,7 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVER_I2C_TPM_ACPI select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select VARIANT_HAS_MIPI_CAMERA @@ -95,32 +98,40 @@ config BOARD_GOOGLE_VOXEL select BOARD_GOOGLE_BASEBOARD_VOLTEER select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_ELEMI select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_VOEMA select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT select VARIANT_HAS_MIPI_CAMERA config BOARD_GOOGLE_DROBIT select BOARD_GOOGLE_BASEBOARD_VOLTEER select DRIVERS_GENESYSLOGIC_GL9755 + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_COPANO select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_GOOGLE_COLLIS select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_VOLET select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_CHRONICLER select BOARD_GOOGLE_BASEBOARD_VOLTEER + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/chronicler/data.vbt b/src/mainboard/google/volteer/variants/chronicler/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/collis/data.vbt b/src/mainboard/google/volteer/variants/collis/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/collis/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/copano/data.vbt b/src/mainboard/google/volteer/variants/copano/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/delbin/data.vbt b/src/mainboard/google/volteer/variants/delbin/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/delbin/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/drobit/data.vbt b/src/mainboard/google/volteer/variants/drobit/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/drobit/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/eldrid/data.vbt b/src/mainboard/google/volteer/variants/eldrid/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/elemi/data.vbt b/src/mainboard/google/volteer/variants/elemi/data.vbt new file mode 100644 index 0000000..f3597e2 --- /dev/null +++ b/src/mainboard/google/volteer/variants/elemi/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/voema/data.vbt b/src/mainboard/google/volteer/variants/voema/data.vbt new file mode 100644 index 0000000..6242c7fd --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/volet/data.vbt b/src/mainboard/google/volteer/variants/volet/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/volteer2/data.vbt b/src/mainboard/google/volteer/variants/volteer2/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer2/data.vbt Binary files differ diff --git a/src/mainboard/google/volteer/variants/voxel/data.vbt b/src/mainboard/google/volteer/variants/voxel/data.vbt new file mode 100644 index 0000000..a7cd7da --- /dev/null +++ b/src/mainboard/google/volteer/variants/voxel/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/74852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Gerrit-Change-Number: 74852 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Correct the number of NID entries
by Martin L Roth (Code Review) 28 Apr '23

28 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74241 ) Change subject: mb/starlabs/starbook/adl: Correct the number of NID entries ...................................................................... mb/starlabs/starbook/adl: Correct the number of NID entries The number of NID entries was too high for the Realtek and Intel sound cards, preventing the verb table from loading. Now the values are correct; it loads as intended. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl/hda_verb.c 1 file changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c index a234de1..c2d10ed 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c @@ -7,7 +7,7 @@ /* coreboot specific header */ 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ 0x1e507007, /* Subsystem ID */ - 36, /* Number of jacks (NID entries) */ + 17, /* Number of jacks (NID entries) */ /* Reset Codec First */ AZALIA_RESET(0x1), @@ -54,7 +54,7 @@ 0x80862815, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ - 9, /* Number of 4 dword sets */ + 10, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x80860101), -- To view, visit https://review.coreboot.org/c/coreboot/+/74241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71 Gerrit-Change-Number: 74241 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap
by Martin L Roth (Code Review) 28 Apr '23

28 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74744 ) Change subject: ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap ...................................................................... ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap Change the fallback value of the `fn_ctrl_swap` option to 0, which is disabled. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/ec/starlabs/merlin/ite.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 9730647..0f807de 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -174,7 +174,7 @@ ec_write(ECRAM_FN_CTRL_REVERSE, get_ec_value_from_option("fn_ctrl_swap", - 1, + 0, fn_ctrl_swap, ARRAY_SIZE(fn_ctrl_swap))); -- To view, visit https://review.coreboot.org/c/coreboot/+/74744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fcbb497f14ed0c97ff05c6c01a3929522786781 Gerrit-Change-Number: 74744 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ec/starlabs/merlin/acpi: Don't attempt to change EC values
by Martin L Roth (Code Review) 28 Apr '23

28 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74186 ) Change subject: ec/starlabs/merlin/acpi: Don't attempt to change EC values ...................................................................... ec/starlabs/merlin/acpi: Don't attempt to change EC values The EC will constantly update the battery variables approximately every 60 seconds; they should be used unmodified, rather than trying to change them. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/ec/starlabs/merlin/acpi/battery.asl 1 file changed, 17 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl index 12aaa74..abdcc5b 100644 --- a/src/ec/starlabs/merlin/acpi/battery.asl +++ b/src/ec/starlabs/merlin/acpi/battery.asl @@ -34,9 +34,6 @@ Method (_BIF, 0, Serialized) { BPKG[1] = B1DC - If (B1FC >= B1DC) { - B1FC = B1DC - } BPKG[2] = B1FC BPKG[4] = B1DV If (B1FC) -- To view, visit https://review.coreboot.org/c/coreboot/+/74186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cff0ac6a322018cbca33b5f90dd62b3475da25c Gerrit-Change-Number: 74186 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Correct port for Hot Plug
by Martin L Roth (Code Review) 28 Apr '23

28 Apr '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74738 ) Change subject: mb/starlabs/starbook/adl: Correct port for Hot Plug ...................................................................... mb/starlabs/starbook/adl: Correct port for Hot Plug Commit 5103b87a4d7b ("mb/starlabs/starbook/adl: Add an option to enable Hot Plug") introduced an option to enable Hot Plug for the SSD. The port was set to 4 (RP5) which is the wireless card. Change this to 8 (RP9) which is the SSD. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/mainboard/starlabs/starbook/variants/adl/ramstage.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c index 7accb1d..a2c3926 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c @@ -11,5 +11,5 @@ * third-party drives are detected. */ if (get_uint_option("pci_hot_plug", 0) == 1) - supd->PcieRpHotPlug[4] = 1; + supd->PcieRpHotPlug[8] = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I884f4997d73e31bd422477952466f168afad66a1 Gerrit-Change-Number: 74738 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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