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Change subject: mb/google/poppy/var/nami: Override SMBIOS product name
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Patch Set 1: Code-Review+1
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Change subject: soc/intel/adl: Unhide PMC, IOM ACPI devices from OS
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Patch Set 1: Code-Review+1
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Change subject: mb/google/hatch: Add SOF chip driver
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Patch Set 3: Code-Review+1
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Change subject: mb/google/volteer: Add VBT data files for variants
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Patch Set 1:
(1 comment)
Patchset:
PS1:
> Most of these files look the same, should we override […]
I didn't notice, I'll add the common one to the baseboard, set as default and override the ones that are different.
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Change subject: mb/google/myst: Inject SPD binaries to APCB
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/myst/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74746/comment/4c54efc0_c07b8016
PS1, Line 18: APCB_PHX_D5
> My question is in regards to PHX (bringup SOC) and the follow-on SOCs that Myst is intending to ship […]
APCB so far is known/expected to be compatible between Phoenix and its refresh SoCs. If there are any unforeseen incompatibilities, then we have to work with AMD and figure out a way to edit the APCB binary (just like how SPD binary is injected here).
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Change subject: soc/amd/common/psp_verstage: Map/unmap boot device on need basis
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Patch Set 1:
(3 comments)
File src/soc/amd/common/psp_verstage/boot_dev.c:
https://review.coreboot.org/c/coreboot/+/74606/comment/1b7df134_c57a96d0
PS1, Line 22: svc_map_spi_rom
> I expect SVC call to not touch mapping on failure. […]
Confirmed that on failure, mapping is untouched. So mapping should be NULL on failure.
https://review.coreboot.org/c/coreboot/+/74606/comment/6964acce_c12ae3e7
PS1, Line 22: size
> Not that I am aware of. I can check with PSP team.
Confirmed through the bug, there is no restriction on size of region to be mapped. There is no alignment restriction on size and offset.
File src/soc/amd/common/psp_verstage/fch.c:
https://review.coreboot.org/c/coreboot/+/74606/comment/20f785a9_e012018d
PS1, Line 100: SpiBiosSmnBase
> Atleast as per the command structure defined in bl_syscall_public.h - https://chromium.googlesource. […]
Done
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Change subject: mb/google/volteer: Add VBT data files for variants
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Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Most of these files look the same, should we override
`config INTEL_GMA_VBT_FILE` instead of keeping copies?
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Change subject: acpi: Add missing cbfs_unmap()
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Patch Set 5: Code-Review+2
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Change subject: soc/amd/common/block/cpu: Add missing cbfs_unmap()
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/74777/comment/99ede524_92b71690
PS3, Line 102: goto end;
I don't think we need a `goto` here, and is hurting readability more than helping simplify the code. I prefer `cbfs_unmap()` with `return` instead, especially since it's branching into the middle of a conditional block.
https://review.coreboot.org/c/coreboot/+/74777/comment/57bb888c_8aa3c208
PS3, Line 113: cbfs_unmap((void *)ucode);
While the `>=` was added to make it more likely that this is called eventually, it also means it's possible for multiple CPUs to execute `cbfs_unmap()` at the same time, corrupting the CBFS cache data structures.
There are a few things here:
1. This should be reverted back to `==`, so it's performed exactly once.
2. We should crash if we see `> get_cpu_count()`, since that indicates we've hit a (likely) fatal error.
3. The access to `ucode` needs to be within an semaphore that's incremented by every reader, so it's only freed once all current readers have completed.
* The `== get_cpu_count()` will need to block until all readers are done, since it's the only one that can safely call `cbfs_unmap()`.
* Otherwise, if the `> get_cpu_count()` case occurs, it's possible for CPUs to be loading microcode while the cache is being freed (and the memory potentially reused, meaning the microcode binary being loaded isn't actually microcode, but "random" data).
* If we ignore the `> get_cpu_count()` case, then we can skip this step, since the atomic counter should be enough to prevent freeing the `ucode` memory until everyone is done with it.
I'm not sure how possible `> get_cpu_count()` is, though. Ideally, we could catch that when releasing the other CPUs (before getting here?), but I don't know the details well enough.
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