coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74840 ) Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail … [View More]

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Kyösti Mälkki, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74839 ) Change subject: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74839 To unsubscribe, or for help … [View More]

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[S] Change in coreboot[master]: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
by Jérémy Compostella (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74805/comment/74f26784_9ce323e2 PS3, Line 7: soc/… [View More]

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[M] Change in coreboot[master]: Documentation/contributing: Add sign-off procedure
by Patrick Georgi (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Paul Menzel, Nicholas Chin. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74825 ) Change subject: Documentation/contributing: Add sign-off procedure ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74825 To unsubscribe, or for help writing mail filters, visit https://… [View More]

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[S] Change in coreboot[master]: Documentation/contributing: Update sign-off procedure
by Patrick Georgi (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Martin L Roth, Paul Menzel, Nicholas Chin. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74851 ) Change subject: Documentation/contributing: Update sign-off procedure ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74851 To unsubscribe, or for help writing mail filters, visit https://review.… [View More]

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[M] Change in coreboot[master]: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex
by Wonkyu Kim (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik, Paul Menzel, Jay Patel. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73192 ) Change subject: mainboard/google/rex/Kconfig: Enable EC boot timestamps for mtl-rex ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73192/comment/0b12ee51_db43ba7f … [View More]

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync
by Jérémy Compostella (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Bora Guvendik, Anil Kumar K, Hannah Williams, Subrata Banik, Paul Menzel, Kapil Porwal, Rizwan Qureshi, Krishna P Bhat D. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74796 ) Change subject: soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/… [View More]

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Tim Van Patten (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 3: (2 comments) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/74736/comment/… [View More]70f0f5ed_d8ba7ad0 PS3, Line 1402: &chip_h[strlen("src/")] > Mainboard path is got from devicetree path which in turn always contains "src/" Contains or starts with "src/"? If it's just 'contains', then this is (essentially) starting at a random location within `mainboard_path`, since the path doesn't start with "src/". If it's 'starts', then please add a comment stating why that's guaranteed to be the case, so we always get a good path starting 4 chars into the string. https://review.coreboot.org/c/coreboot/+/74736/comment/80f0d4aa_7908ac97 PS3, Line 1405: free(mainboard_path); > I think the memory location immediately preceding the allocated/freed address will have some metadat […] Everything I'm reading states that double-freeing is undefined behavior (at best) and corrupts the memory allocation structures at worst. Where do you see that it's safe to double-free memory? -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 21:24:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment [View Less]

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Tim Van Patten, Angel Pons, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 3: (2 comments) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/74736/comment/… [View More]9fb6c9b7_8477c265 PS3, Line 1402: &chip_h[strlen("src/")] > I don't understand this indexing into `chip_h`. […] Mainboard path is got from devicetree path which in turn always contains "src/". I thought about adding check for src/ substring and am still open to it. But if the path is going to contain src/ always, that check might be redundant. https://review.coreboot.org/c/coreboot/+/74736/comment/0df70f80_02dba5c7 PS3, Line 1405: free(mainboard_path); > This is potentially a double-free, since `mainboard_path` does not always allocate its own memory (r […] I think the memory location immediately preceding the allocated/freed address will have some metadata to help with freeing. From that standpoint, even if mainboard_path is just referencing the address it is fine to use it during free. Note: mainboard_path is still pointing to the start of the allocated buffer (same as allocated in base_devtree_path/dir). -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:51:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment [View Less]

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[M] Change in coreboot[master]: soc/intel/common/gpio: Add open-drain GPIO macros
by Nick Vaccaro (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Cliff Huang. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74841 ) Change subject: soc/intel/common/gpio: Add open-drain GPIO macros ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/74841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/… [View More]

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coreboot-gerrit April 2023