coreboot-gerrit April 2023

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[S] Change in coreboot[master]: sb,soc/amd,intel: Drop include <cpu/x86/smm.h>
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Kyösti Mälkki, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74811 ) Change subject: sb,soc/amd,intel: Drop include <cpu/x86/smm.h> ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Gerrit-Change-Number: 74811 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 01:14:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common/gpio: Add open-drain GPIO macros
by Julius Werner (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Cliff Huang, Nick Vaccaro. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74841 ) Change subject: soc/intel/common/gpio: Add open-drain GPIO macros ...................................................................... Patch Set 1: (1 comment) File src/include/gpio.h: https://review.coreboot.org/c/coreboot/+/74841/comment/1bff86a1_ac3a61f1 PS1, Line 18: void gpio_set_HiZ(gpio_t gpio_num); I don't really think these belong here in the platform-independent API as separate calls. Usually the way we do things is that we have platform-specific functions that can configure the GPIO in the right mode (e.g. whether it's open-drain or push-pull), and then calling gpio_set() on it should do the right thing for the respective mode. Alternatively, you can basically consider gpio_input() the equivalent of gpio_set_HiZ(), and gpio_input_pulldown() the equivalent of gpio_od_set(..., 0) (and then pullup -> 1). -- To view, visit https://review.coreboot.org/c/coreboot/+/74841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca9915c7574e741c20af2e8dc91f6a07f7c0d26 Gerrit-Change-Number: 74841 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 01:01:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc'lpc: simplify index handling in read resources
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74849 ) Change subject: soc/amd/common/block/lpc'lpc: simplify index handling in read resources ...................................................................... soc/amd/common/block/lpc'lpc: simplify index handling in read resources Now that we don't need to find a specific resource in the set resources function any more, there's no need to use hard-coded indices for the fixed resources. Instead use an index variable that gets incremented after each fixed resource got added. The index now starts at 0 instead of at 1, but now the only requirement is that those indices are unique. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 22 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/74849/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 79a1d59..3d5775f 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -106,6 +106,7 @@ static void lpc_read_resources(struct device *dev) { struct resource *res; + unsigned long idx = 0; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -118,20 +119,20 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ - mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE, + mmio_range(dev, idx++, FLASH_BELOW_4GB_MAPPING_REGION_BASE, FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); + mmio_range(dev, idx++, SPI_BASE_ADDRESS, 4 * KiB); /* Add a memory resource for the eSPI MMIO */ - mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); + mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB); /* FCH IOAPIC */ - mmio_range(dev, 4, IO_APIC_ADDR, 4 * KiB); + mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB); /* HPET */ - mmio_range(dev, 5, HPET_BASE_ADDRESS, 4 * KiB); + mmio_range(dev, idx++, HPET_BASE_ADDRESS, 4 * KiB); compact_resources(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32 Gerrit-Change-Number: 74849 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74848 ) Change subject: soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources ...................................................................... soc/amd/common/block/lpc/lpc: drop custom lpc_set_resources Drop the custom lpc_set_resources implementation that does some register access that has no effect and then calls pci_dev_set_resources and use pci_dev_set_resources for set_resources in amd_lpc_ops instead. The SPI controller's base address got configured early in boot in the lpc_set_spibase call and the enable bits got set early in boot in the lpc_enable_spi_rom call. TEST=The contents of the SPI_BASE_ADDRESS_REGISTER at the beginning and at the end of the call stay the same, so it's simply a no-op. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74848/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 3da3266..79a1d59 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -136,21 +136,6 @@ compact_resources(dev); } -static void lpc_set_resources(struct device *dev) -{ - struct resource *res; - u32 spi_enable_bits; - - /* Special case. The SpiRomEnable and other enables should STAY set. */ - res = find_resource(dev, 2); - spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); - spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; - pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, - res->base | spi_enable_bits); - - pci_dev_set_resources(dev); -} - static void configure_child_lpc_windows(struct device *dev, struct device *child) { struct resource *res; @@ -329,7 +314,7 @@ struct device_operations amd_lpc_ops = { .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = lpc_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = lpc_acpi_name, -- To view, visit https://review.coreboot.org/c/coreboot/+/74848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a5e3e00b2e38eeb3e9dae6d6c83d11ef925ce22 Gerrit-Change-Number: 74848 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: security/tpm: Add Kconfig to allow payload control of TPM1
by Julius Werner (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Matt DeVillier, Christian Walter. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74856 ) Change subject: security/tpm: Add Kconfig to allow payload control of TPM1 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: How is this practically different from just not enabling CONFIG_TPM1 at all (and letting the payload do everything, from TPM_Startup)? Sending the Startup in coreboot but then keeping the TPM disabled/deactivated, doesn't seem very useful, because then (IIRC?) it doesn't accept any commands (e.g. PCR extensions for measured boot), so you don't really get anything out of having done the Startup so early. I think the only really practically useful configurations are either that you want coreboot to set up and use your TPM (which means it must enable and activate it), or that you want coreboot to not touch your TPM at all and do everything from the payload, and I think both of those should already be possible with the existing options. -- To view, visit https://review.coreboot.org/c/coreboot/+/74856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Gerrit-Change-Number: 74856 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 00:52:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report HPET MMIO
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: use mmio_range to report FCH IOAPIC MMIO
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report eSPI MMIO
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74844 ) Change subject: soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte ...................................................................... soc/amd/common/block/lpc/lpc: increase size of SPI BAR to 4kByte The memory map granularity for those devices is 4kByte. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/74844/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923..5b836ea 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -121,7 +121,7 @@ FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); + mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB); res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; -- To view, visit https://review.coreboot.org/c/coreboot/+/74844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8806128bdce8988f5cd7c8fa8a342fdb01eb7f42 Gerrit-Change-Number: 74844 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: security/tpm: Add Kconfig to allow payload control of TPM1
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Christian Walter. Hello Christian Walter, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74856 to look at the new patch set (#2). Change subject: security/tpm: Add Kconfig to allow payload control of TPM1 ...................................................................... security/tpm: Add Kconfig to allow payload control of TPM1 Normally, for TPM1, coreboot will force activate/enable the TPM if TPM_DEACTIVATE is not selected, but this is not desirable in the case that the payload needs to be able to control activation/deactivation/ take ownership etc. Add a Kconfig to allow opting out of this forced enablement. TEST=build/boot google/lulu with edk2, verify TPM can be enabled/ disabled/cleared from payload TPM menu. Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74856/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Gerrit-Change-Number: 74856 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2023