coreboot-gerrit April 2023

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[S] Change in coreboot[master]: security/tpm: Add Kconfig to allow payload control of TPM1
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Christian Walter, Julius Werner. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74856 ) Change subject: security/tpm: Add Kconfig to allow payload control of TPM1 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > How is this practically different from just not enabling CONFIG_TPM1 at all (and letting the payload […] if CONFIG_TPM1 isn't selected, then you're selecting CONFIG_NO_TPM. I haven't tested it, but without TPM1, I'm pretty sure there's a bunch of ACPI left out of the SSDT, particularly related to PP. But I will re-test and see if that works sufficiently well. -- To view, visit https://review.coreboot.org/c/coreboot/+/74856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Gerrit-Change-Number: 74856 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 29 Apr 2023 02:54:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device()
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74440 ) Change subject: asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() ...................................................................... asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() FADT duty_width/duty_offset fields, together with P_CNT (previously P_BLK) IO address are provided with _PTC entry. FADT p_lvl2/3_lat fields had values that disabled C2/C3 state transitions so _CST entries are not required. Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74440 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/fadt.c 2 files changed, 24 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index a4cd1b3..a9b9949 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -8,10 +8,12 @@ static void generate_cpu_entry(int cpu) { - int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6; + acpigen_write_processor_device(cpu); - acpigen_write_processor(cpu, pcontrol_blk, plen); - acpigen_pop_len(); + /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ + acpigen_write_PTC(3, 1, DEFAULT_PMBASE + PCNTRL); + + acpigen_write_processor_device_end(); } void generate_cpu_entries(const struct device *device) diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 43e119b..551ec8f 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -29,9 +29,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4; - fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ - fadt->duty_width = 3; /* this width is in bits */ - /* * bit meaning * 0 1: We have user-visible legacy devices -- To view, visit https://review.coreboot.org/c/coreboot/+/74440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629cd0793f6a64e955e197400efaa7d9d898e775 Gerrit-Change-Number: 74440 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73212 ) Change subject: mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup ...................................................................... mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startup Add functionality to ensure that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). -Confirmed power is off for 150ms on boot. -Confirmed RCC_CSR of FPMCU indicates power cycle occurred. -Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and timings are as expected. Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nami/mainboard.c 2 files changed, 104 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 68f0f5b..58c02b8 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -404,7 +404,7 @@ /* B1 : CORE_VID1 ==> FPMCU_INT_L */ PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ - PAD_CFG_GPO(GPP_B11, 1, DEEP), + PAD_CFG_GPO(GPP_B11, 0, DEEP), /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ @@ -416,13 +416,47 @@ /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ PAD_CFG_GPO(GPP_C3, 0, DEEP), /* C9 : UART0_TXD ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_C9, 1, DEEP), + PAD_CFG_GPO(GPP_C9, 0, DEEP), /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_D5, 0, DEEP), /* D17 : DMIC_CLK1 ==> NC */ PAD_NC(GPP_D17, NONE), }; +const struct pad_config *variant_romstage_sku_gpio_table(size_t *num) +{ + uint32_t sku_id = variant_board_sku(); + const struct pad_config *board_gpio_tables; + + switch (sku_id) { + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + *num = ARRAY_SIZE(fpmcu_gpio_table); + board_gpio_tables = fpmcu_gpio_table; + break; + default: + /* Initialized in variant_sku_gpio_table */ + *num = 0; + board_gpio_tables = NULL; + break; + } + return board_gpio_tables; +} + const struct pad_config *variant_sku_gpio_table(size_t *num) { uint32_t sku_id = variant_board_sku(); @@ -468,8 +502,8 @@ case SKU_5_BARD: case SKU_6_BARD: case SKU_7_BARD: - *num = ARRAY_SIZE(fpmcu_gpio_table); - board_gpio_tables = fpmcu_gpio_table; + *num = 0; + board_gpio_tables = NULL; break; default: *num = ARRAY_SIZE(nami_default_sku_gpio_table); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index b703d40..a4634fc 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -15,6 +15,8 @@ #include <soc/ramstage.h> #include <string.h> #include <variant/sku.h> +#include <gpio.h> +#include <delay.h> #define PL2_I7_SKU 44 #define PL2_DEFAULT 29 @@ -299,3 +301,36 @@ sku_overwrite_mapping[oem_index].dc_loadline[i]; } } + +void variant_final(void) +{ + uint32_t sku_id = variant_board_sku(); + + switch (sku_id) { + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + case SKU_4_BARD: + case SKU_5_BARD: + case SKU_6_BARD: + case SKU_7_BARD: + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + case SKU_4_EKKO: + case SKU_5_EKKO: + case SKU_6_EKKO: + case SKU_7_EKKO: + /* Enable FPMCU late in the boot process to achieve + * ~150ms of power off time in total. + */ + gpio_output(GPP_B11, 1); /* PCH_FP_PWR_EN */ + mdelay(3); + gpio_output(GPP_C9, 1); /* FP_RST_ODL */ + break; + default: + break; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Gerrit-Change-Number: 73212 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/poppy: Add support for variant SKU romstage GPIO configs
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73211 ) Change subject: mb/google/poppy: Add support for variant SKU romstage GPIO configs ...................................................................... mb/google/poppy: Add support for variant SKU romstage GPIO configs Add functionality that allows a variant SKU to have a specific set of GPIO configs in romstage (modeled after the existing one in ramstage) BUG=b:245954151 TEST=builds Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/romstage.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h 3 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/poppy/romstage.c b/src/mainboard/google/poppy/romstage.c index 7fd4409..f73ca5f9 100644 --- a/src/mainboard/google/poppy/romstage.c +++ b/src/mainboard/google/poppy/romstage.c @@ -140,6 +140,8 @@ pads = variant_romstage_gpio_table(&num); gpio_configure_pads(pads, num); + pads = variant_romstage_sku_gpio_table(&num); + gpio_configure_pads(pads, num); memset(&p, 0, sizeof(p)); variant_memory_params(&p); diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 9048e29..ee2b1dc 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -383,6 +383,13 @@ return NULL; } +const struct pad_config * __weak + variant_romstage_sku_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h index 9e4bfc5..603a2ba 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h @@ -21,6 +21,7 @@ /* Config gpio by different sku id */ const struct pad_config *variant_sku_gpio_table(size_t *num); +const struct pad_config *variant_romstage_sku_gpio_table(size_t *num); enum memory_type { MEMORY_LPDDR3, -- To view, visit https://review.coreboot.org/c/coreboot/+/73211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Gerrit-Change-Number: 73211 Gerrit-PatchSet: 9 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex/variants/screebo: Generate RAM IDs
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74802 ) Change subject: mb/google/rex/variants/screebo: Generate RAM IDs ...................................................................... mb/google/rex/variants/screebo: Generate RAM IDs Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/memory/Makefile.inc M src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt 3 files changed, 41 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc index eace2e4..c46681a 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc +++ b/src/mainboard/google/rex/variants/screebo/memory/Makefile.inc @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/screebo/memory src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = MT62F1G32D2DS-026 WT:B, H58G56BK7BX068 diff --git a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt index fa24790..be70745 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen MTL lp5 src/mainboard/google/rex/variants/screebo/memory src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 0 (0000) +MT62F1G32D2DS-026 WT:B 1 (0001) +H58G56BK7BX068 1 (0001) diff --git a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt index 9621137..8027588 100644 --- a/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt +++ b/src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +MT62F1G32D2DS-026 WT:B +H58G56BK7BX068 -- To view, visit https://review.coreboot.org/c/coreboot/+/74802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Gerrit-Change-Number: 74802 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/stoney/acpi: Unhide PCI0 root device from OS
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74855 ) Change subject: soc/amd/stoney/acpi: Unhide PCI0 root device from OS ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: oh, i didn't expect that to be the problem. good catch! -- To view, visit https://review.coreboot.org/c/coreboot/+/74855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Gerrit-Change-Number: 74855 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 02:28:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Derek Huang, Paul Menzel, Kapil Porwal, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74783 ) Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74783/comment/aaf9303e_8df90707 PS2, Line 14: Ideally FSP API should be able to return the status (both success and : error code) upon exiting the FSP API but unfortunately there are some : scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return : any ERROR status. Hence, this function provides an additional hook to : read the FSP reset status by reading the dedicated HOB without relying : on the FSP API exit status code. > > Is there an FSP upstream bug report for this? If yes, it’d be great if you referenced it. > > the bug being mentioned in the commit msg is the own assigned to Intel and there will be external communication from Intel Ping! Patchset: PS5: @Kapil, if you can take a look into the latest patch ? -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 02:14:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
by Subrata Banik (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Tarun Tuli, Jérémy Compostella, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74805/comment/69809987_13f1c2b7 PS3, Line 7: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise > soc/intel/cmn/cse: Do CSE sync by default in romstage CSE sync in rommstage was the default theme anyway. the purpose of this CL is to drop the hard coding (set to default Y) and relying on the ramstage cse sync config to set the default CSE sync behavior. In order to narrate the difference I have added `unless ramstage chooses otherwise` in the commit msg -- To view, visit https://review.coreboot.org/c/coreboot/+/74805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Gerrit-Change-Number: 74805 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 02:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb,soc/amd,intel: Drop include <cpu/x86/smm.h>
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74811 ) Change subject: sb,soc/amd,intel: Drop include <cpu/x86/smm.h> ...................................................................... sb,soc/amd,intel: Drop include <cpu/x86/smm.h> I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT entries for SMI architectural"). Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 17 files changed, 18 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Elyes Haouas: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index ee344cc..46afe53 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -13,7 +13,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 221e7df..90cfef9 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -16,7 +16,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 0adf659..edb0c13 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -15,7 +15,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 9a30225..049033b 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -16,7 +16,6 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/amd/cpuid.h> -#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <types.h> diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 38dcaff..35c2b43 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -11,7 +11,6 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/amd/cpuid.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <gpio.h> diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dc64e66..21a4834 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -10,7 +10,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> -#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <gpio.h> diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 18ae68b..de89ef1 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <soc/iomap.h> #include <soc/pm.h> #include "chip.h" diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index b3cbd7e..d057d21 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index f67ab37..8b79ec9 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <soc/iomap.h> #include <soc/pm.h> #include "chip.h" diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index e65e24d..db31e9e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -11,7 +11,6 @@ #include <cpu/intel/msr.h> #include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/smm.h> #include <intelblocks/acpi_wake_source.h> #include <intelblocks/acpi.h> #include <intelblocks/lpc_lib.h> diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index b0d719f..c7d5428 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmutil.h> #include "chip.h" diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 56c3cc7..4245e12 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <device/pci_ops.h> void acpi_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 0da488d..98861c5 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmbase.h> #include "i82801gx.h" #include "chip.h" diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index ee861fd..f8cca2d 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index ca5dfeb..e7a9104 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmutil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 44ee59a..bae209d 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/common/pmutil.h> #include "chip.h" diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index d83c58f..dc7ee54 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -2,7 +2,6 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> -#include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/pch.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/74811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35 Gerrit-Change-Number: 74811 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Make FADT entries for RTC/CMOS architectural
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74601 ) Change subject: ACPI: Make FADT entries for RTC/CMOS architectural ...................................................................... ACPI: Make FADT entries for RTC/CMOS architectural For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/acpi.c M src/arch/x86/acpi.c M src/include/pc80/mc146818rtc.h M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/include/soc/acpi.h M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/include/soc/acpi.h M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/include/soc/acpi.h M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/include/soc/acpi.h M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 29 files changed, 39 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e06ac47..a57d498 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1748,9 +1748,6 @@ fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); - if (CONFIG(USE_PC_CMOS_ALTCENTURY)) - fadt->century = RTC_CLK_ALTCENTURY; - fadt->sci_int = acpi_sci_int(); arch_fill_fadt(fadt); diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index e1ef978..ffa3463 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <cf9_reset.h> #include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> void arch_fill_fadt(acpi_fadt_t *fadt) { @@ -24,4 +25,14 @@ fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } + + if (CONFIG(PC80_SYSTEM)) { + /* Currently these are defined to support date alarm only. */ + fadt->day_alrm = RTC_DATE_ALARM; + fadt->mon_alrm = RTC_MONTH_ALARM; + } + + /* Careful with USE_OPTION_TABLE. */ + if (CONFIG(USE_PC_CMOS_ALTCENTURY)) + fadt->century = RTC_CLK_ALTCENTURY; } diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 2f94cc0..383c41f 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -93,6 +93,9 @@ #define RTC_CLK_YEAR 9 #define RTC_CLK_ALTCENTURY 0x32 +#define RTC_DATE_ALARM RTC_REG_D +#define RTC_MONTH_ALARM 0 + /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 #define PC_CKS_RANGE_END 45 diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 07cdcbf..ee344cc 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -50,8 +50,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/cezanne/include/soc/acpi.h b/src/soc/amd/cezanne/include/soc/acpi.h index ab90c96..1a0e2a1 100644 --- a/src/soc/amd/cezanne/include/soc/acpi.h +++ b/src/soc/amd/cezanne/include/soc/acpi.h @@ -10,11 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index df86296..221e7df 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -52,8 +52,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/glinda/include/soc/acpi.h b/src/soc/amd/glinda/include/soc/acpi.h index 69e2f87..138086e 100644 --- a/src/soc/amd/glinda/include/soc/acpi.h +++ b/src/soc/amd/glinda/include/soc/acpi.h @@ -12,11 +12,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 7e703c0..0adf659 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -51,8 +51,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/mendocino/include/soc/acpi.h b/src/soc/amd/mendocino/include/soc/acpi.h index 45e8a1b..ac3c490 100644 --- a/src/soc/amd/mendocino/include/soc/acpi.h +++ b/src/soc/amd/mendocino/include/soc/acpi.h @@ -10,11 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 09d7b8b..9a30225 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -52,8 +52,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; - fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/phoenix/include/soc/acpi.h b/src/soc/amd/phoenix/include/soc/acpi.h index dc09a1d..823b9ce8 100644 --- a/src/soc/amd/phoenix/include/soc/acpi.h +++ b/src/soc/amd/phoenix/include/soc/acpi.h @@ -12,11 +12,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d -#define RTC_ALT_CENTURY 0x32 -#define RTC_CENTURY 0x48 - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 366751f..38dcaff 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -56,7 +56,6 @@ fill_fadt_extended_pm_regs(fadt); - fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 741b732..3b83123 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -10,9 +10,6 @@ #define ACPI_SCI_IRQ 9 -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d - uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp); diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index b3895b3..dc64e66 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -54,7 +54,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index 302416e..0065d6e 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -14,9 +14,6 @@ #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) #endif -/* RTC Registers */ -#define RTC_DATE_ALARM 0x0d - const char *soc_acpi_name(const struct device *dev); #endif /* AMD_STONEYRIDGE_ACPI_H */ diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 8a2831b..18ae68b 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -22,8 +22,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 526f797..b3cbd7e 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -23,8 +23,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 9a4c036..f67ab37 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -22,8 +22,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 32; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 9722881..e65e24d 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -106,7 +106,6 @@ /* GPE0 STS/EN pairs each 32 bits wide. */ fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); - fadt->day_alrm = 0xd; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 39dbd4a..fc00dcb 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -47,8 +47,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - /* RTC Registers */ - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; /* PM2 Control Registers */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index dfe9986..ff46857 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -38,8 +38,6 @@ fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index e76682d..b0d719f 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -25,8 +25,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 00e204e..43e119b 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -31,8 +31,7 @@ fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ - fadt->mon_alrm = 0x0; /* not supported */ + /* * bit meaning * 0 1: We have user-visible legacy devices diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index e5ad336..56c3cc7 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -19,8 +19,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 8; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index ccbc504..0da488d 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -33,8 +33,7 @@ fadt->duty_width = 3; else fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index bcd7d90..ee861fd 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -26,8 +26,7 @@ fadt->p_lvl3_lat = 0x39; fadt->duty_offset = 1; fadt->duty_width = 3; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index 73d7ea0..ca5dfeb 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -26,8 +26,7 @@ fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */ fadt->duty_offset = 1; fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES; fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index d750890..44ee59a 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -25,8 +25,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index eaea091..d83c58f 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -37,8 +37,6 @@ else fadt->gpe0_blk_len = 2 * 8; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->flags |= ACPI_FADT_WBINVD | -- To view, visit https://review.coreboot.org/c/coreboot/+/74601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Gerrit-Change-Number: 74601 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2023