coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: mb/starlabs/starbook: Let coreboot configure ASPM
by Lean Sheng Tan (Code Review) 29 Apr '23

29 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74520 ) Change subject: mb/starlabs/starbook: Let coreboot configure ASPM ...................................................................... mb/starlabs/starbook: Let coreboot configure ASPM FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205) but coreboot's configuration results in lower power consumption of approximately 0.5W when idling - the reason why is unknown. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb 2 files changed, 18 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 5ad7e27..b49a86d 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -147,30 +147,9 @@ string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" -config PCIEXP_ASPM - bool - default n - help - FSP is already taking care of ASPM, which is configured through the devicetree in coreboot - on Alderlake Platforms. Disable it to save some boot time. - config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS default 32 -config PCIEXP_L1_SUB_STATE - bool - default n - help - Enabling PCIe L1 sub states is already done in FSP. - Disable it to save some boot time. - -config PCIEXP_CLK_PM - bool - default n - help - Enabling PCIe clock power management is already done in FSP. - Disable it to save some boot time - config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 5c54f4d..298ec19 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -100,8 +100,6 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -119,8 +117,6 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_aspm = ASPM_L0S_L1, }" smbios_slot_desc "SlotTypeM2Socket3" -- To view, visit https://review.coreboot.org/c/coreboot/+/74520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250 Gerrit-Change-Number: 74520 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Lance Zhao, Caveh Jalali, Tim Wawrzynczak, Kyösti Mälkki, Boris Mittelberg. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74524 ) Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/auron/smihandler.c: https://review.coreboot.org/c/coreboot/+/74524/comment/5dd7c592_407addeb PS6, Line 39: chromeec_set_usb_charge_mode(slp_typ); > Seems to me like these are all using GNVS for no reason at all, seems to be a static board customisation value that does not change runtime? yes, it's very odd, not sure why it was done this way -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sat, 29 Apr 2023 15:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Update intel-sec-tools submodule to upstream master
by Elyes Haouas (Code Review) 29 Apr '23

29 Apr '23

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74322 ) Change subject: Update intel-sec-tools submodule to upstream master ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I705c89a1ba36b9d10c5f2326c02d3e37e9a263f6 Gerrit-Change-Number: 74322 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: acpi/acpigen.h: Drop deprecated ACPI OP codes
by build bot (Jenkins) (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72757 ) Change subject: acpi/acpigen.h: Drop deprecated ACPI OP codes ...................................................................... Patch Set 8: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175275): https://review.coreboot.org/c/coreboot/+/72757/comment/7288c1e3_2ccd0a50 PS8, Line 9: Clean up OP codes according to ACPI specs: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51e7f8dc6c0bfef0816ab4da6d96cb0fac873ee8 Gerrit-Change-Number: 72757 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 29 Apr 2023 14:17:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/intel/kblrvp: Clean smihandler
by Kyösti Mälkki (Code Review) 29 Apr '23

29 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74861 ) Change subject: mb/intel/kblrvp: Clean smihandler ...................................................................... mb/intel/kblrvp: Clean smihandler Change-Id: I0ada381883aa65d36434486dcce6b2331599e5c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/kblrvp/smihandler.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74861/1 diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index c6f4239..4e9524d 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -22,9 +22,8 @@ void mainboard_smi_sleep(u8 slp_typ) { if (CONFIG(EC_GOOGLE_CHROMEEC)) - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, - MAINBOARD_EC_S5_WAKE_EVENTS); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); } int mainboard_smi_apmc(u8 apmc) -- To view, visit https://review.coreboot.org/c/coreboot/+/74861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ada381883aa65d36434486dcce6b2331599e5c3 Gerrit-Change-Number: 74861 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/jecht: Clean smihandler
by Kyösti Mälkki (Code Review) 29 Apr '23

29 Apr '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74860 ) Change subject: mb/google/jecht: Clean smihandler ...................................................................... mb/google/jecht: Clean smihandler Change-Id: I47ec05aa87e4e7c02b19817b2f703eca492008e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/jecht/smihandler.c 1 file changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/74860/1 diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index a4feeb4..54666da 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> -#include <ec/google/chromeec/ec.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include <soc/iomap.h> #include "onboard.h" @@ -31,14 +30,3 @@ break; } } - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APM_CNT_ACPI_ENABLE: - break; - case APM_CNT_ACPI_DISABLE: - break; - } - return 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/74860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47ec05aa87e4e7c02b19817b2f703eca492008e6 Gerrit-Change-Number: 74860 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: protectcli/vault_bsw: Drop USB power control bits in GNVS
by Kyösti Mälkki (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Michał Żygowski, Piotr Król. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74859 ) Change subject: protectcli/vault_bsw: Drop USB power control bits in GNVS ...................................................................... protectcli/vault_bsw: Drop USB power control bits in GNVS There is no platform-level implementation for USB port power management in various sleepstates. This mainboard never evaluates the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers. Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/protectli/vault_bsw/acpi_tables.c 1 file changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/74859/1 diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c index 4206cde..4276be7 100644 --- a/src/mainboard/protectli/vault_bsw/acpi_tables.c +++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c @@ -1,15 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <acpi/acpi_gnvs.h> -#include <soc/acpi.h> -#include <soc/nvs.h> - -void mainboard_fill_gnvs(struct global_nvs *gnvs) -{ - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; -} +#include <acpi/acpi.h> void mainboard_fill_fadt(acpi_fadt_t *fadt) { -- To view, visit https://review.coreboot.org/c/coreboot/+/74859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c Gerrit-Change-Number: 74859 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mainboard/*: Drop USB power control bits in GNVS
by Kyösti Mälkki (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Evgeny Zinoviev. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74858 ) Change subject: mainboard/*: Drop USB power control bits in GNVS ...................................................................... mainboard/*: Drop USB power control bits in GNVS There is no platform-level implementation for USB port power management in various sleepstates. The mainboards changed here never evaluate the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI handlers. Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/apple/macbookair4_2/gnvs.c M src/mainboard/bostentech/gbyt4/acpi_tables.c M src/mainboard/facebook/fbg1701/acpi_tables.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/dcp847ske/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/portwell/m107/acpi_tables.c 9 files changed, 15 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74858/1 diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c index 5ec2f712..8ba9667 100644 --- a/src/mainboard/apple/macbookair4_2/gnvs.c +++ b/src/mainboard/apple/macbookair4_2/gnvs.c @@ -5,14 +5,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* the lid is open by default. */ gnvs->lids = 1; diff --git a/src/mainboard/bostentech/gbyt4/acpi_tables.c b/src/mainboard/bostentech/gbyt4/acpi_tables.c index dc0d7a2..d53e97c 100644 --- a/src/mainboard/bostentech/gbyt4/acpi_tables.c +++ b/src/mainboard/bostentech/gbyt4/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* TPM not present */ gnvs->tpmp = 0; diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c index 3576455..d5dc5cc 100644 --- a/src/mainboard/facebook/fbg1701/acpi_tables.c +++ b/src/mainboard/facebook/fbg1701/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 33f4b6b..83e3165 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -8,14 +8,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* TPM Present */ gnvs->tpmp = 1; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 189f7f4..bc8ce27 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -9,12 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->tmps = TEMPERATURE_SENSOR_ID; gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 927f7bc..675f732 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -9,17 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* - * Enable Front USB ports in S5 by default - * to be consistent with back port behavior - */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - /* TPM Present */ gnvs->tpmp = 1; diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c index b8d4421..64f3f04 100644 --- a/src/mainboard/intel/dcp847ske/acpi_tables.c +++ b/src/mainboard/intel/dcp847ske/acpi_tables.c @@ -6,14 +6,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 by default */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Enable USB ports in S5 by default */ - gnvs->s5u0 = 1; - gnvs->s5u1 = 1; - gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index c6d4ce8..d24238d 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -9,12 +9,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c index 3576455..d5dc5cc 100644 --- a/src/mainboard/portwell/m107/acpi_tables.c +++ b/src/mainboard/portwell/m107/acpi_tables.c @@ -7,14 +7,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) { - /* Enable USB ports in S3 */ - gnvs->s3u0 = 1; - gnvs->s3u1 = 1; - - /* Disable USB ports in S5 */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - /* PMIC is configured in I2C1, hide it for the OS */ struct device_nvs *dev_nvs = acpi_get_device_nvs(); dev_nvs->lpss_en[LPSS_NVS_I2C2] = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/74858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Gerrit-Change-Number: 74858 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: [WIP] ACPI: Add usb_charge_mode_from_gnvs()
by Kyösti Mälkki (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Lance Zhao, Caveh Jalali, Matt DeVillier, Tim Wawrzynczak, Boris Mittelberg. Hello Lance Zhao, build bot (Jenkins), Caveh Jalali, Paul Menzel, Tim Wawrzynczak, Boris Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74524 to look at the new patch set (#7). Change subject: [WIP] ACPI: Add usb_charge_mode_from_gnvs() ...................................................................... [WIP] ACPI: Add usb_charge_mode_from_gnvs() Used together with (old API?) of ChromeEC to control USB port power for S3/S5 sleep states. This changes adds USB power control for S4 behave the same as for S5. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Kconfig M src/acpi/acpi_pm.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/smm.h M src/include/acpi/acpi_gnvs.h M src/mainboard/google/auron/Kconfig M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/butterfly/acpi_tables.c M src/mainboard/google/butterfly/smihandler.c M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/acpi_tables.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/link/Kconfig M src/mainboard/google/link/acpi_tables.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/parrot/Kconfig M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/Kconfig M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/slippy/Kconfig M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/Kconfig M src/mainboard/google/stout/acpi_tables.c M src/mainboard/google/stout/smihandler.c M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/soc/intel/broadwell/include/soc/nvs.h 34 files changed, 110 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/74524/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/74524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Gerrit-Change-Number: 74524 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Put options in CFR cbtable
by Angel Pons (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Sean Rhodes, Christian Walter, Angel Pons, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Benjamin Doron, Christian Walter, Maximilian Brune, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74122 to look at the new patch set (#3). Change subject: [WIP] mb/prodrive/atlas: Put options in CFR cbtable ...................................................................... [WIP] mb/prodrive/atlas: Put options in CFR cbtable PLEASE REMOVE THE TESTONLY OPTIONS IF BUILDING THIS FOR PRODUCTION YOU HAVE BEEN WARNED Open questions: - What to do with payload-specific options? The payload needs to know about them anyway, so describing them in coreboot kind of defeats the purpose of avoiding duplication. In our case, we can handle the profile values in the payload, which coreboot can send through CFR. - Hook up options using the option API - Figure out the details for some options (e.g. LLC dead line alloc) - Figure out if any options are missing, and if the defaults are OK The plan is to avoid having to specify the options in both edk2 and coreboot. Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/Makefile.inc A src/mainboard/prodrive/atlas/cfr.c 3 files changed, 301 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/74122/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47585a9a6f94ab5005f2ab63a0df267c0caef231 Gerrit-Change-Number: 74122 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023