coreboot-gerrit April 2023

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[S] Change in coreboot[master]: security/tpm: Add Kconfig to allow payload control of TPM1
by build bot (Jenkins) (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Christian Walter. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74856 ) Change subject: security/tpm: Add Kconfig to allow payload control of TPM1 ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175242): https://review.coreboot.org/c/coreboot/+/74856/comment/f9896b75_9e15b798 PS1, Line 9: Normally, for TPM1, coreboot will force activate/enable the TPM if 'desireable' may be misspelled - perhaps 'desirable'? -- To view, visit https://review.coreboot.org/c/coreboot/+/74856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Gerrit-Change-Number: 74856 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 23:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/tpm: Add Kconfig to allow payload control of TPM1
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74856 ) Change subject: security/tpm: Add Kconfig to allow payload control of TPM1 ...................................................................... security/tpm: Add Kconfig to allow payload control of TPM1 Normally, for TPM1, coreboot will force activate/enable the TPM if TPM_DEACTIVATE is not selected, but this is not desireable in the case that the payload needs to be able to control activation/deactivation/ take ownership etc. Add a Kconfig to allow opting out of this forced enablement. TEST=build/boot google/lulu with edk2, verify TPM can be enabled/ disabled/cleared from payload TPM menu. Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74856/1 diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 39134c1..c89d4f9 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -59,6 +59,14 @@ help Deactivate TPM by issuing deactivate command. +config TPM_PAYLOAD_CONTROL + bool "Allow payload control of TPM" + default n + depends on !VBOOT && !TPM_DEACTIVATE + depends on TPM1 + help + Allows the payload to handle activation/deactivation of TPM. + config DEBUG_TPM bool "Output verbose TPM debug messages" default n diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index a771d2a..ed871f0 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -181,7 +181,8 @@ } #if CONFIG(TPM1) - result = tpm1_invoke_state_machine(); + if (!CONFIG(TPM_PAYLOAD_CONTROL)) + result = tpm1_invoke_state_machine(); #endif if (CONFIG(TPM_MEASURED_BOOT)) result = tspi_measure_cache_to_pcr(); -- To view, visit https://review.coreboot.org/c/coreboot/+/74856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb7db109cbcc1a0166d95b6130b624b635bb7ac9 Gerrit-Change-Number: 74856 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/stoney/acpi: Unhide PCI0 root device from OS
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74855 ) Change subject: soc/amd/stoney/acpi: Unhide PCI0 root device from OS ...................................................................... soc/amd/stoney/acpi: Unhide PCI0 root device from OS In order for Windows to detect/load drivers for any child devices, the PCI0 root device status must be enabled and visible. TEST=build google/liara, boot Windows, verify PCI child devices visible in Device Manager. Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/northbridge.asl 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/74855/1 diff --git a/src/soc/amd/stoneyridge/acpi/northbridge.asl b/src/soc/amd/stoneyridge/acpi/northbridge.asl index 7ed6225..c47b7b7 100644 --- a/src/soc/amd/stoneyridge/acpi/northbridge.asl +++ b/src/soc/amd/stoneyridge/acpi/northbridge.asl @@ -15,7 +15,7 @@ Method(_STA, 0, NotSerialized) { - Return(0x0B) /* Status is visible */ + Return(0x0F) /* Status is visible */ } Method(_PRT,0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/74855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fb1ba11247f0811120a4cf8a4fd99342ae201de Gerrit-Change-Number: 74855 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: commit-msg: Match the Signed-off-by line with name and mail address
by Paul Menzel (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Bao Zheng, Angel Pons, Zheng Bao. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73340 ) Change subject: commit-msg: Match the Signed-off-by line with name and mail address ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73340/comment/06d8a12b_003acb30 PS1, Line 8: Please describe the problem, and maybe give an example where the hook failed, so it needed this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/73340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166 Gerrit-Change-Number: 73340 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Fri, 28 Apr 2023 23:06:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Tim Van Patten, Angel Pons, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 4: (1 comment) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/74736/comment/218209e9_accfcc2e PS3, Line 1402: &chip_h[strlen("src/")] > > Mainboard path is got from devicetree path which in turn always contains "src/" […] Done. Added code to handle that condition so that it is clear where to look for when things don't meet the expectation. -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 22:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74736 to look at the new patch set (#4). Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... util/sconfig: Include optional maiboard chip header Mainboard chip headers can contain definitions that can be referenced in the devicetree. One of the potential use-cases is for the hardware configurations in devicetree to refer to net names instead of cryptic GPIO numbers. This helps to improve the code readability. Add support to include mainboard chip header, if present. BUG=None TEST=Build Skyrim BIOS with & without mainboard chip header. Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M util/sconfig/main.c 1 file changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74736/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by Felix Held (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74840 ) Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/lpc/lpc.c: https://review.coreboot.org/c/coreboot/+/74840/comment/77f5512c_ca905076 PS2, Line 117: IORESOURCE_FIXED i'm not sure about the IORESOURCE_FIXED flag. when adding subtractive domain MMIO resources, the IORESOURCE_FIXED flag mustn't be set. if IORESOURCE_FIXED is set in the subtractive domain resources to tel lthe resource allocator where it may put non-fixed mmio resources, we get this error DOMAIN: 0000: Resource ranges: * EMPTY!! and after that also some NULL dereferences -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 Gerrit-Change-Number: 74840 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 22:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache
by Karthik Ramasubramanian (Code Review) 29 Apr '23

29 Apr '23

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73257 ) Change subject: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache ...................................................................... soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS directory entry in RO with that section. If the RECOVERY_MRC_CACHE section is not present, then fall back to RW_MRC_CACHE. BUG=b:270569389 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73257 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc 2 files changed, 34 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 48fd2a5..6df8fe7 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -8,6 +8,7 @@ select ACPI_SOC_NVS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH + select CACHE_MRC_SETTINGS select DRIVERS_USB_ACPI select DRIVERS_USB_PCI_XHCI select FSP_COMPRESS_FSP_M_LZMA if !ASYNC_FILE_LOADING diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index a40aa2c..0945830 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -135,6 +135,16 @@ APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) +# On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. +# Else use RW_MRC_CACHE. This entry will be added in the RO section. +APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +else +APOB_NV_RO_SIZE=$(APOB_NV_SIZE) +APOB_NV_RO_BASE=$(APOB_NV_BASE) +endif + ifeq ($(CONFIG_AMDFW_SPLIT),y) FMAP_AMDFW_BODY_LOCATION=$(shell awk '$$2 == "FMAP_SECTION_AMDFWBODY_START" {print $$3}' $(obj)/fmap_config.h) endif @@ -191,6 +201,8 @@ OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_APOB_NV_RO_SIZE=$(call add_opt_prefix, $(APOB_NV_RO_SIZE), --apob-nv-size) +OPT_APOB_NV_RO_BASE=$(call add_opt_prefix, $(APOB_NV_RO_BASE),--apob-nv-base) OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) @@ -245,8 +257,8 @@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB_NV_SIZE) \ - $(OPT_APOB_NV_BASE) \ + $(OPT_APOB_NV_RO_SIZE) \ + $(OPT_APOB_NV_RO_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/73257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Gerrit-Change-Number: 73257 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Tim Van Patten (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Karthik Ramasubramanian, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74736 ) Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... Patch Set 3: (2 comments) File util/sconfig/main.c: https://review.coreboot.org/c/coreboot/+/74736/comment/9c6a2379_eb41539d PS3, Line 1405: free(mainboard_path); > Everything I'm reading states that double-freeing is undefined behavior (at best) and corrupts the m […] Chatted offline, I was getting lost. This is only freeing once, since `mainboard_path` = `base_devtree_dir` = `base_devtree_path`, and the other `free` only occurs when that's not the case. https://review.coreboot.org/c/coreboot/+/74736/comment/32408d3a_83a3be02 PS3, Line 2030: mainboard_path = base_devtree_dir; > ref1 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 22:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache
by Matt DeVillier (Code Review) 29 Apr '23

29 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73257 ) Change subject: soc/amd/phoenix: Populate type 0x63 entry with right MRC Cache ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5ac87685eaa5fec717e3efa4df7af511b4ce8aa Gerrit-Change-Number: 73257 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 22:03:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023