coreboot-gerrit April 2023

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[M] Change in coreboot[master]: util/sconfig: Include optional maiboard chip header
by Karthik Ramasubramanian (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held. Hello build bot (Jenkins), Raul Rangel, Martin L Roth, Jon Murphy, Arthur Heymans, Angel Pons, Tim Van Patten, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74736 to look at the new patch set (#2). Change subject: util/sconfig: Include optional maiboard chip header ...................................................................... util/sconfig: Include optional maiboard chip header Mainboard chip headers can contain defintions that can be referenced in the devicetree. One of the potential use-cases is for the hardware configurations in devicetree to refer to net names instead of cryptic GPIO numbers. This helps to improve the code readability. Add support to include mainboard chip header, if present. BUG=None TEST=Build Skyrim BIOS with & without mainboard chip header. Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M util/sconfig/main.c 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74736/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34893a703cc4f588dda3736e858429bf765059e6 Gerrit-Change-Number: 74736 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by build bot (Jenkins) (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74840 ) Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175228): https://review.coreboot.org/c/coreboot/+/74840/comment/5e0ec998_34fe2380 PS1, Line 19: PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags 40040100 index 10000000 Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175228): https://review.coreboot.org/c/coreboot/+/74840/comment/76606760_d8b7778c PS1, Line 20: PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags 40040100 index 10000100 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 Gerrit-Change-Number: 74840 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:10:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74840 ) Change subject: soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC ...................................................................... soc/amd/common/block/lpc/lpc: don't report PCI config IO ports in LPC The 2*4 IO ports from 0xcf8 to 0xcff are used for the IO-based PCI config space access, so they wont be decoded to the LPC device and the devices below it, so split the subtractive IO range of the LPC device that those IO ports aren't covered by the subtractive IO regions of the LPC device. TEST=The coreboot console output on mandolin now shows the two subtractive IO regions on the LPC device instead of the one that also covered the PCI config IO ports: PCI: 00:14.3 resource base 0 size 0 align 0 gran 0 limit cf7 flags 40040100 index 10000000 PCI: 00:14.3 resource base d00 size 0 align 0 gran 0 limit fff flags 40040100 index 10000100 The contents of /proc/mem are still identical. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 37 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/74840/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index b8fb923..4a1151a 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -109,12 +109,21 @@ /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O. */ + /* Add subtractive resource for IO ports 0x0000 to 0x0cf7 */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; - res->size = 0x1000; + res->limit = PCI_IO_CONFIG_INDEX - 1; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + IORESOURCE_ASSIGNED; + + /* IO ports 0x0cf8 to 0x0cff are used for PCI config space access */ + + /* Add subtractive resource for IO ports 0x0d00 to 0x0fff */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = PCI_IO_CONFIG_INDEX + 2 * 4; + res->limit = 0x1000 - 1; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE, -- To view, visit https://review.coreboot.org/c/coreboot/+/74840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67458dd14fa89d223e97c2410484c08654a6fab8 Gerrit-Change-Number: 74840 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74839 ) Change subject: soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range ...................................................................... soc/amd/common/block/lpc/lpc: report mapped SPI flash as MMIO range Since the 16MByte of memory-mapped SPI flash region right below the 4GB boundary is both a fixed region and isn't decoded on a device below the LPC device, but assumed to be decoded by the LPC device itself, it shouldn't be reported as a subtractive resource, but as an MMIO resource instead. TEST=On mandolin the 16MByte MMIO-mapped SPI flash now show up as a reserved region in the e820 memory map which wasn't the case before: 13. 00000000ff000000-00000000ffffffff: RESERVED The Linux kernel doesn't show any new or possibly related errors. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/74839/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 1fbff53..b8fb923 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -117,11 +117,8 @@ IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = FLASH_BELOW_4GB_MAPPING_REGION_BASE; - res->size = FLASH_BELOW_4GB_MAPPING_REGION_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE, + FLASH_BELOW_4GB_MAPPING_REGION_SIZE); /* Add a memory resource for the SPI BAR. */ mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/74839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52df2b2d79a1e6213c3499984a5a1e0e25c058a Gerrit-Change-Number: 74839 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/volteer: Add VBT data files for variants
by Nico Huber (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74852 ) Change subject: mb/google/volteer: Add VBT data files for variants ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS1: > I didn't notice, I'll add the common one to the baseboard, set as default and override the ones that […] Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/74852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Gerrit-Change-Number: 74852 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Apr 2023 20:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util: Use common ARRAY_SIZE define
by Felix Held (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Konrad Adamczyk, Jakub Czapiga, Christian Walter. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74474 ) Change subject: util: Use common ARRAY_SIZE define ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: i wonder if the intention to not use that define in util/ was so that the tools can be build outside of the coreboot tree. not sure whom to ask about this though -- To view, visit https://review.coreboot.org/c/coreboot/+/74474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3 Gerrit-Change-Number: 74474 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 28 Apr 2023 19:32:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74809 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct PCI MMIO BAR window ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec Gerrit-Change-Number: 74809 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 18:55:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Martin Roth, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74804 ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Gerrit-Change-Number: 74804 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 28 Apr 2023 18:55:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/volteer: Add VBT data files for variants
by Matt DeVillier (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Nico Huber, Nick Vaccaro. Hello build bot (Jenkins), Nico Huber, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74852 to look at the new patch set (#2). Change subject: mb/google/volteer: Add VBT data files for variants ...................................................................... mb/google/volteer: Add VBT data files for variants Add data.vbt files for all variants supported by current volteer recovery image. Several boards use the same VBT, so put it under the baseboard and make it the default; those which do not use the "common" VBT override and use the one in their own variant dir. Select INTEL_GMA_HAVE_VBT for all variants which have a VBT file. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/volteer/Kconfig A src/mainboard/google/volteer/variants/baseboard/data.vbt A src/mainboard/google/volteer/variants/elemi/data.vbt A src/mainboard/google/volteer/variants/voema/data.vbt 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/74852/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Gerrit-Change-Number: 74852 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: vc/google: Decouple DSM_CALIB from CHROMEOS
by CoolStar (Code Review) 28 Apr '23

28 Apr '23

Attention is currently required from: Tarun Tuli, Matt DeVillier, Nick Vaccaro. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74812 ) Change subject: vc/google: Decouple DSM_CALIB from CHROMEOS ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Gerrit-Change-Number: 74812 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Apr 2023 17:23:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023