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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
mb/google/myst: Enable PCIe devices in devicetree
Ensure that DXIO descriptors are updated using info from AMD and Myst board
schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/port_descriptors.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
3 files changed, 103 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/20
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 10:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173237):
https://review.coreboot.org/c/coreboot/+/74099/comment/fc67399f_6155206b
PS10, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173237):
https://review.coreboot.org/c/coreboot/+/74099/comment/bd94d3bd_11abbf66
PS10, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
mb/google/myst: First pass GPIO configuration for Myst
Initial GPIO configuration for Myst.
BUG=b:270596581
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b
---
M src/mainboard/google/myst/variants/baseboard/gpio.c
1 file changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74095/9
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Hello build bot (Jenkins), Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#14).
Change subject: soc/intel/cmn: Implement API to retrieve firmware partition information
......................................................................
soc/intel/cmn: Implement API to retrieve firmware partition information
This patch retrieves details of a specified firmware partition. The
information retrieved includes the mkhi header, current firmware
version, and other information about the partition. The patch
communicates with the ME using the HECI command to acquire this
information.
BUG=b:273661726
Test=Verified the changes for ISHC partition on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/14
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 16:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/74110/comment/f8291398_0446947a
PS6, Line 29: .op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
> Please add a TODO(b/276913952) to bump this back up to 33MHz once things seem to be working well.
Done
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/66fb4905_8350a74e
PS7, Line 116: /* SPI_SOC_DO_TCHSCR_DO_R */
: PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE),
> Looks like this is misnamed here. […]
Done
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Change subject: mb/google/rex: Enable audio BT offload
......................................................................
Patch Set 15:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72881/comment/db089406_9f44bfe8
PS13, Line 10: SSP1 needs to be used for BT offload and program vGPIO.
> Yes . I2S0 and I2S2 lines are being used for speaker adn HP connections on daughter board. […]
Done
https://review.coreboot.org/c/coreboot/+/72881/comment/c2f2a026_b6a9f02b
PS13, Line 13: TEST=Playback through BT
> 1. Did BT work before? […]
we have added the details in partner bug
Patchset:
PS13:
> BT offload was verified on Rex with I2S audio configuration […]
Done
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/74099/comment/d51b9885_3e7d9c09
PS5, Line 26: | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
> Still missing `EC_HOST_EVENT_BODY_DETECT_CHANGE`.
Done
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