coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 ) Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post" ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74206/comment/dd636aeb_f1ed1aa0 PS1, Line 11: Revert initial change as it was causing a boot failure when transitioning : into recovery mode. wrap up text? -- To view, visit https://review.coreboot.org/c/coreboot/+/74206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Gerrit-Change-Number: 74206 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:49:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
by Tarun Tuli (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Subrata Banik, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74207 ) Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Gerrit-Change-Number: 74207 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:48:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
by Tarun Tuli (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Subrata Banik, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 ) Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Gerrit-Change-Number: 74206 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:48:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 ) Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post" ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173301): https://review.coreboot.org/c/coreboot/+/74206/comment/3eac8dc0_4cb7babb PS1, Line 10: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Gerrit-Change-Number: 74206 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:46:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
by Nick Vaccaro (Code Review) 04 Apr '23

04 Apr '23

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74207 ) Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" ...................................................................... Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c. This initial change was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c 3 files changed, 55 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74207/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 33d703f..f1f53d6 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -67,25 +67,6 @@ Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. -config SOC_INTEL_CSE_SEND_EOP_ASYNC - bool - depends on SOC_INTEL_COMMON_BLOCK_CSE - depends on !SOC_INTEL_CSE_SEND_EOP_LATE - depends on !SOC_INTEL_CSE_SEND_EOP_EARLY - help - Use this config to handle End Of Post (EOP) completion - asynchronously. The EOP command is sent first and the result - is checked later leaving time to CSE to complete the - operation while coreboot perform other activities. - Performing EOP asynchronously reduces the time spent - actively waiting for command completion which can have a - significant impact on boot time. - - Using this asynchronous approach comes with the limitation - that no HECI command should be sent between the time the EOP - request is posted (at CSE .final device operation) and the - time coreboot check for its completion (BS_PAYLOAD_LOAD). - config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 6c4bb73..9902094 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1407,8 +1407,7 @@ */ void cse_late_finalize(void) { - if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) && - !CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) return; if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) @@ -1432,14 +1431,6 @@ if (CONFIG(SOC_INTEL_CSE_SET_EOP)) cse_send_end_of_post(); - /* - * In asynchronous mode, the EOP command has most likely not been - * completed yet. Finalization steps will be run once the EOP command - * has successfully been completed. - */ - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) - return; - if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) cse_final_ready_to_boot(); diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 16cf523..53a4fa5 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -67,54 +67,13 @@ return CSE_CMD_RESULT_SUCCESS; } -static enum cse_cmd_result cse_receive_eop(void) +static enum cse_cmd_result cse_send_eop(void) { + enum cse_tx_rx_status ret; enum { EOP_REQUESTED_ACTION_CONTINUE = 0, EOP_REQUESTED_ACTION_GLOBAL_RESET = 1, }; - enum cse_tx_rx_status ret; - struct end_of_post_resp { - struct mkhi_hdr hdr; - uint32_t requested_actions; - } __packed resp = {}; - size_t resp_size = sizeof(resp); - - ret = heci_receive(&resp, &resp_size); - if (ret) - return decode_heci_send_receive_error(ret); - - if (resp.hdr.group_id != MKHI_GROUP_ID_GEN || - resp.hdr.command != MKHI_END_OF_POST) { - printk(BIOS_ERR, "HECI: EOP Unexpected response group or command.\n"); - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) - printk(BIOS_ERR, "HECI: It could be a HECI command conflict.\n"); - return CSE_CMD_RESULT_ERROR; - } - - if (resp.hdr.result) { - printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); - return CSE_CMD_RESULT_ERROR; - } - - printk(BIOS_INFO, "CSE: EOP requested action: "); - - switch (resp.requested_actions) { - case EOP_REQUESTED_ACTION_GLOBAL_RESET: - printk(BIOS_INFO, "global reset\n"); - return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; - case EOP_REQUESTED_ACTION_CONTINUE: - printk(BIOS_INFO, "continue boot\n"); - return CSE_CMD_RESULT_SUCCESS; - default: - printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); - return CSE_CMD_RESULT_ERROR; - } -} - -static enum cse_cmd_result cse_send_eop(void) -{ - enum cse_tx_rx_status ret; struct end_of_post_msg { struct mkhi_hdr hdr; } __packed msg = { @@ -123,6 +82,11 @@ .command = MKHI_END_OF_POST, }, }; + struct end_of_post_resp { + struct mkhi_hdr hdr; + uint32_t requested_actions; + } __packed resp = {}; + size_t resp_size = sizeof(resp); /* For a CSE-Lite SKU, if the CSE is running RO FW and the board is running vboot in recovery mode, the CSE is expected to be in SOFT @@ -155,22 +119,28 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - ret = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + ret = heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR); if (ret) return decode_heci_send_receive_error(ret); - return CSE_CMD_RESULT_SUCCESS; -} + if (resp.hdr.result) { + printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); + return CSE_CMD_RESULT_ERROR; + } -static enum cse_cmd_result cse_send_and_receive_eop(void) -{ - enum cse_cmd_result ret; + printk(BIOS_INFO, "CSE: EOP requested action: "); - ret = cse_send_eop(); - if (ret != CSE_CMD_RESULT_SUCCESS) - return ret; - - return cse_receive_eop(); + switch (resp.requested_actions) { + case EOP_REQUESTED_ACTION_GLOBAL_RESET: + printk(BIOS_INFO, "global reset\n"); + return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; + case EOP_REQUESTED_ACTION_CONTINUE: + printk(BIOS_INFO, "continue boot\n"); + return CSE_CMD_RESULT_SUCCESS; + default: + printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); + return CSE_CMD_RESULT_ERROR; + } } static enum cse_cmd_result cse_send_cmd_retries(enum cse_cmd_result (*cse_send_command)(void)) @@ -229,12 +199,11 @@ } } -static void do_send_end_of_post(bool wait_for_completion) +static void do_send_end_of_post(void) { - static bool eop_sent = false, eop_complete = false; - enum cse_cmd_result ret; + static bool eop_sent = false; - if (eop_complete) { + if (eop_sent) { printk(BIOS_WARNING, "EOP already sent\n"); return; } @@ -253,40 +222,26 @@ return; } - if (!eop_sent) { - set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); - timestamp_add_now(TS_ME_END_OF_POST_START); - ret = cse_send_cmd_retries(cse_send_eop); - if (ret == CSE_CMD_RESULT_SUCCESS) - eop_sent = true; - } - - if (!wait_for_completion) - return; - set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); - ret = cse_receive_eop(); - if (ret != CSE_CMD_RESULT_SUCCESS) { - ret = cse_send_cmd_retries(cse_send_and_receive_eop); - handle_cse_eop_result(ret); - } + + timestamp_add_now(TS_ME_END_OF_POST_START); + handle_cse_eop_result(cse_send_cmd_retries(cse_send_eop)); timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); - eop_complete = true; + eop_sent = true; } void cse_send_end_of_post(void) { - return do_send_end_of_post(!CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)); + return do_send_end_of_post(); } static void send_cse_eop_with_late_finalize(void *unused) { - do_send_end_of_post(true); - if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || - CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) + do_send_end_of_post(); + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) cse_late_finalize(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/74207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Gerrit-Change-Number: 74207 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
by Nick Vaccaro (Code Review) 04 Apr '23

04 Apr '23

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74206 ) Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post" ...................................................................... Revert "mb/google/brya: Enable asynchronous End-Of-Post" This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74206/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e588524..9ae944d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -32,7 +32,6 @@ select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2887439..1bc84ce 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -122,7 +122,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON + select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE -- To view, visit https://review.coreboot.org/c/coreboot/+/74206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Gerrit-Change-Number: 74206 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/intel/cmn/cse: Handle unnecessary End-Of-Post
by Jérémy Compostella (Code Review) 04 Apr '23

04 Apr '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74205 ) Change subject: soc/intel/cmn/cse: Handle unnecessary End-Of-Post ...................................................................... soc/intel/cmn/cse: Handle unnecessary End-Of-Post BUG:b/276927816 BRANCH=firmware-brya-14505.B TEST=local tests - TBD Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74205/1 diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 16cf523..1317a72 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -19,6 +19,7 @@ CSE_CMD_RESULT_ERROR, CSE_CMD_RESULT_DISABLED, CSE_CMD_RESULT_RETRY, + CSE_CMD_RESULT_SKIP, }; static enum cse_cmd_result decode_heci_send_receive_error(enum cse_tx_rx_status ret) @@ -131,7 +132,7 @@ cse_is_hfs1_com_soft_temp_disable()) { printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " "TEMP DISABLE state, skipping EOP\n"); - return CSE_CMD_RESULT_SUCCESS; + return CSE_CMD_RESULT_SKIP; } /* @@ -259,6 +260,9 @@ ret = cse_send_cmd_retries(cse_send_eop); if (ret == CSE_CMD_RESULT_SUCCESS) eop_sent = true; + /* End-Of-Post is not needed. */ + if (ret == CSE_CMD_RESULT_SKIP) + goto done; } if (!wait_for_completion) @@ -270,8 +274,9 @@ ret = cse_send_cmd_retries(cse_send_and_receive_eop); handle_cse_eop_result(ret); } - timestamp_add_now(TS_ME_END_OF_POST_END); +done: + timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); eop_complete = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/74205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046 Gerrit-Change-Number: 74205 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Fred Reitberger (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 7: (2 comments) File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/735baf3a_5bbdf63d PS2, Line 2: SI_BIOS { > Fred, Why is the MRC region increasing? I would like to understand since the memory technology is th […] I'd have to check with the ABL team to know why the APOB increased. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/3fabd9dc_6be50f38 PS3, Line 36: } > Given the lack of clarity on how things are looking for 32 MB SPI support, do you think we can addre […] A 16 MB layout for a first pass should be fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Add smihandler
by Karthik Ramasubramanian (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Eric Lai, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74100 ) Change subject: mb/google/myst: Add smihandler ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Gerrit-Change-Number: 74100 Gerrit-PatchSet: 15 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:12:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/myst: Enable chromeOS EC
by Karthik Ramasubramanian (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Eric Lai, Tim Van Patten, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74099 ) Change subject: mb/google/myst: Enable chromeOS EC ...................................................................... Patch Set 12: Code-Review+2 (1 comment) File src/mainboard/google/myst/ec.c: https://review.coreboot.org/c/coreboot/+/74099/comment/cd62bb58_e2c281c8 PS12, Line 4: #include <console/console.h> Not required yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/74099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Gerrit-Change-Number: 74099 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 18:11:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023