coreboot-gerrit April 2023

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Handle unnecessary End-Of-Post
by Nick Vaccaro (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jérémy Compostella. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74205 ) Change subject: soc/intel/cmn/cse: Handle unnecessary End-Of-Post ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046 Gerrit-Change-Number: 74205 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 19:36:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Eric Lai, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/myst/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74093/comment/c7720e06_316227bc PS2, Line 16: Name(LIDS, 0) > I didn't see who use this in AMD SoC code. And this is in chrome EC LID device code. https://source. […] The LIDS object is used by the EC and not by the SoC. the code you linked is the bit inside the chrome EC's EMEM; the LIDS object is separate from that. IIRC the \LIDS = LIDS statement copies the data from one into the other; both have different scopes. the LIDS object doesn't need to be in GNVS and is also not used by the SoC itself, so i removed it from the AMD SoC's GNVS and added it to the Chromebook's DSDT file. The better solution would be to move the LIDS object to the EC code too, but reworking that is very much out of scope for me, since it's now only in Intel SoC and different EC code. right now there's nothing to do here; this is a possible future improvement though -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 19:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
by Kapil Porwal (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Nick Vaccaro. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74207 ) Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Gerrit-Change-Number: 74207 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 19:26:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
by Kapil Porwal (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Nick Vaccaro. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 ) Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Gerrit-Change-Number: 74206 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 19:26:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Handle unnecessary End-Of-Post
by Jérémy Compostella (Code Review) 04 Apr '23

04 Apr '23

Jérémy Compostella has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/74205 ) Change subject: soc/intel/cmn/cse: Handle unnecessary End-Of-Post ...................................................................... soc/intel/cmn/cse: Handle unnecessary End-Of-Post BUG:b/276927816 BRANCH=firmware-brya-14505.B TEST=local tests - TBD Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74205/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046 Gerrit-Change-Number: 74205 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86/64bit/Makefile: use all_x86 make target
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74197 ) Change subject: cpu/x86/64bit/Makefile: use all_x86 make target ...................................................................... cpu/x86/64bit/Makefile: use all_x86 make target Use the newly introduced 'all_x86' make target to add the mode_switch.S compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8950375d31557d9a38169869c1d250417261c31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74197 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/cpu/x86/64bit/Makefile.inc 1 file changed, 18 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/cpu/x86/64bit/Makefile.inc b/src/cpu/x86/64bit/Makefile.inc index 526291a..36c69b9 100644 --- a/src/cpu/x86/64bit/Makefile.inc +++ b/src/cpu/x86/64bit/Makefile.inc @@ -1,8 +1,4 @@ -bootblock-y += mode_switch.S -verstage_x86-y += mode_switch.S -romstage-y += mode_switch.S -postcar-y += mode_switch.S -ramstage-y += mode_switch.S +all_x86-y += mode_switch.S # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/pt.S $(obj)/config.h -- To view, visit https://review.coreboot.org/c/coreboot/+/74197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8950375d31557d9a38169869c1d250417261c31c Gerrit-Change-Number: 74197 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/64bit/Makefile: use verstage_x86 make target
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74196 ) Change subject: cpu/x86/64bit/Makefile: use verstage_x86 make target ...................................................................... cpu/x86/64bit/Makefile: use verstage_x86 make target Use the 'verstage_x86' make target for the mode_switch.S compilation unit instead of making adding it to the 'verstage' target depending on VBOOT_STARTS_BEFORE_BOOTBLOCK not being selected. The only case where VBOOT_STARTS_BEFORE_BOOTBLOCK is selected is the verstage on PSP case, so I find using the 'verstage_x86' target here a bit easier to understand. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iab618d4b9e325b07a648b91fcdce99c63644fbfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/74196 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/64bit/Makefile.inc 1 file changed, 21 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/cpu/x86/64bit/Makefile.inc b/src/cpu/x86/64bit/Makefile.inc index 48f56fc..526291a 100644 --- a/src/cpu/x86/64bit/Makefile.inc +++ b/src/cpu/x86/64bit/Makefile.inc @@ -1,7 +1,5 @@ bootblock-y += mode_switch.S -ifneq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -verstage-y += mode_switch.S -endif +verstage_x86-y += mode_switch.S romstage-y += mode_switch.S postcar-y += mode_switch.S ramstage-y += mode_switch.S -- To view, visit https://review.coreboot.org/c/coreboot/+/74196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab618d4b9e325b07a648b91fcdce99c63644fbfc Gerrit-Change-Number: 74196 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/pc80/pc/Makefile: use all_x86 make target
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74153 ) Change subject: drivers/pc80/pc/Makefile: use all_x86 make target ...................................................................... drivers/pc80/pc/Makefile: use all_x86 make target Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74153 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/pc80/pc/Makefile.inc 1 file changed, 21 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/pc80/pc/Makefile.inc b/src/drivers/pc80/pc/Makefile.inc index 63ed998..7cf2957 100644 --- a/src/drivers/pc80/pc/Makefile.inc +++ b/src/drivers/pc80/pc/Makefile.inc @@ -6,11 +6,7 @@ ramstage-$(CONFIG_SPKMODEM) += spkmodem.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c -bootblock-y += i8254.c -verstage_x86-y += i8254.c -romstage-y += i8254.c -ramstage-y += i8254.c -postcar-y += i8254.c +all_x86-y += i8254.c smm-y += i8254.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23c6977ae8acebb8dcd546f86f7f7b677272a6cb Gerrit-Change-Number: 74153 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74152 ) Change subject: cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target ...................................................................... cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74152 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/lapic/Makefile.inc M src/cpu/x86/pae/Makefile.inc M src/cpu/x86/tsc/Makefile.inc 3 files changed, 24 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 22bd987..308e9b2 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -4,14 +4,6 @@ romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c -bootblock-y += boot_cpu.c -verstage_x86-y += boot_cpu.c -romstage-y += boot_cpu.c -ramstage-y += boot_cpu.c -postcar-y += boot_cpu.c -bootblock-y += lapic.c -verstage_x86-y += lapic.c -romstage-y += lapic.c -ramstage-y += lapic.c -postcar-y += lapic.c +all_x86-y += boot_cpu.c +all_x86-y += lapic.c diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc index 70e0b2f..331b5a8 100644 --- a/src/cpu/x86/pae/Makefile.inc +++ b/src/cpu/x86/pae/Makefile.inc @@ -1,6 +1,2 @@ -bootblock-y += pgtbl.c -verstage_x86-y += pgtbl.c -romstage-y += pgtbl.c -postcar-y += pgtbl.c -ramstage-y += pgtbl.c +all_x86-y += pgtbl.c smm-y += pgtbl.c diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 978d7fa..18ce4db 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,6 +1,2 @@ -bootblock-y += delay_tsc.c -ramstage-y += delay_tsc.c -romstage-y += delay_tsc.c -verstage_x86-y += delay_tsc.c -postcar-y += delay_tsc.c +all_x86-y += delay_tsc.c smm-y += delay_tsc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822 Gerrit-Change-Number: 74152 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/*/Makefile: use all_x86 target
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74151 ) Change subject: soc/amd/*/Makefile: use all_x86 target ...................................................................... soc/amd/*/Makefile: use all_x86 target Use the newly introduced 'all_x86' make target to add the compilation unit to all stages that run on the x86 cores, but not to verstage on PSP. TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush with verstage on PSP result in identical images with and without this patch applied. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74151 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/acpi/Makefile.inc M src/soc/amd/common/block/alink/Makefile.inc M src/soc/amd/common/block/cpu/tsc/Makefile.inc M src/soc/amd/common/block/lpc/Makefile.inc M src/soc/amd/common/block/pci/Makefile.inc M src/soc/amd/common/block/pm/Makefile.inc M src/soc/amd/common/block/uart/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Makefile.inc 12 files changed, 55 insertions(+), 97 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index bf57698..062a19d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -9,18 +9,15 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c - -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -28,11 +25,9 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index cf1e9c1..a0d9290 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,11 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y) -bootblock-y += acpi.c -verstage_x86-y += acpi.c -romstage-y += acpi.c -ramstage-y += acpi.c -postcar-y += acpi.c +all_x86-y += acpi.c smm-y += acpi.c ramstage-y += pm_state.c diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index fbb96ee..ef0728a 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,11 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y) -bootblock-y += alink.c -verstage_x86-y += alink.c -romstage-y += alink.c -postcar-y += alink.c -ramstage-y += alink.c +all_x86-y += alink.c smm-y += alink.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index 65e849a..4ec0e0f 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -1,24 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 6bec843..11de514 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -3,20 +3,13 @@ ramstage-y += lpc.c -bootblock-y += lpc_util.c -verstage_x86-y += lpc_util.c -romstage-y += lpc_util.c -postcar-y += lpc_util.c -ramstage-y += lpc_util.c +all_x86-y += lpc_util.c smm-y += lpc_util.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) -bootblock-y += spi_dma.c -verstage_x86-y += spi_dma.c -romstage-y += spi_dma.c -ramstage-y += spi_dma.c +all_x86-y += spi_dma.c smm-y += spi_dma.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index b938c67..372c6ce 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -11,10 +11,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y) -bootblock-y += amd_pci_mmconf.c -verstage_x86-y += amd_pci_mmconf.c -romstage-y += amd_pci_mmconf.c -postcar-y += amd_pci_mmconf.c -ramstage-y += amd_pci_mmconf.c +all_x86-y += amd_pci_mmconf.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc index de1809a..cae4099 100644 --- a/src/soc/amd/common/block/pm/Makefile.inc +++ b/src/soc/amd/common/block/pm/Makefile.inc @@ -1,13 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c - -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc index de7b68e..bd182d9 100644 --- a/src/soc/amd/common/block/uart/Makefile.inc +++ b/src/soc/amd/common/block/uart/Makefile.inc @@ -1,12 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) -# all-y can't be used, since verstage on PSP has a different implementation -bootblock-y += uart.c -verstage_x86-y += uart.c -romstage-y += uart.c -postcar-y += uart.c -ramstage-y += uart.c +all_x86-y += uart.c smm-$(CONFIG_DEBUG_SMI) += uart.c all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 81033e9..47c121e 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -12,19 +12,17 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -32,10 +30,8 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 5ed8386..9d9adce 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -9,19 +9,17 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -30,10 +28,8 @@ ramstage-y += fch.c ramstage-y += fsp_misc_data_hob.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += mca.c ramstage-y += root_complex.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 27e5abc..a40aa2c 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -12,20 +12,18 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c bootblock-y += espi_util.c -bootblock-y += gpio.c -bootblock-y += uart.c verstage-y += espi_util.c -verstage_x86-y += gpio.c -verstage_x86-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c romstage-y += soc_util.c -romstage-y += uart.c ramstage-y += acpi.c ramstage-y += agesa_acpi.c @@ -33,12 +31,10 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += root_complex.c ramstage-y += soc_util.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += gpio.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b5957b9..cb42582 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -10,17 +10,14 @@ all-y += config.c all-y += i2c.c +# all_x86-y adds the compilation unit to all stages that run on the x86 cores +all_x86-y += gpio.c +all_x86-y += uart.c + bootblock-y += early_fch.c -bootblock-y += gpio.c -bootblock-y += uart.c romstage-y += fsp_m_params.c -romstage-y += gpio.c romstage-y += romstage.c -romstage-y += uart.c - -verstage_x86-y += gpio.c -verstage_x86-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c @@ -28,14 +25,12 @@ ramstage-y += cpu.c ramstage-y += fch.c ramstage-y += fsp_s_params.c -ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += pcie_gpp.c ramstage-y += root_complex.c ramstage-y += sata.c ramstage-y += soc_util.c -ramstage-y += uart.c ramstage-y += xhci.c smm-y += smihandler.c -- To view, visit https://review.coreboot.org/c/coreboot/+/74151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1 Gerrit-Change-Number: 74151 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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