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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 13: Code-Review+1
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/a16c7ac7_ae664e21
PS11, Line 111: SPI_SOC_DI_FPMCU_DO_R
> If you look at the schematic https://ee-schematics.teams.x20web.corp.google. […]
I see. Thanks for the explanation.
Is it safe to update the spreadsheet with these names then, to keep everything consistent?
https://docs.google.com/spreadsheets/d/1otkDb3R0ggaSoQcI4nRw9v07Jeb37JXZbjj…
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 13:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/46d2ac53_432cae03
PS11, Line 111: SPI_SOC_DI_FPMCU_DO_R
> Why were these updated to `FPMCU`? […]
If you look at the schematic https://ee-schematics.teams.x20web.corp.google.com/myst/myst/proto0/referen…
The SPI connections are mutually exclusive and can be used for fingerprint or touchscreen. The bug in the TODO is showing that we need to selectively init.
For Myst, fingerprint can be a UART or a SPI variant. Touchscreens can be I2C or SPI, but we have decided not to build devices with SPI enabled touchscreens for our reference. See b/273170012#comment7
In this case both these lines and the lines below are for FPMCU, but depend on which FPMCU we've installed. The touchscreen lines are pulled out to test points and are not actually connected to the SoC.
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 15:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173356):
https://review.coreboot.org/c/coreboot/+/74099/comment/70e11884_a1b5341a
PS15, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173356):
https://review.coreboot.org/c/coreboot/+/74099/comment/773bbc6a_62bc4e87
PS15, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Change subject: mb/google/myst: Add new mainboard
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Patch Set 9:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173350):
https://review.coreboot.org/c/coreboot/+/74093/comment/fe509a8d_21721d8b
PS9, Line 7: const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
need consistent spacing around '*' (ctx:WxO)
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Change subject: mb/google/myst: Enable AP <-> GSC communication
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Patch Set 25: Code-Review+1
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 14:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173335):
https://review.coreboot.org/c/coreboot/+/74099/comment/88222f60_33381237
PS14, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173335):
https://review.coreboot.org/c/coreboot/+/74099/comment/cd7ca9b5_45c156f9
PS14, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Change subject: amd/mendocino/root_complex: Restrict DPTC to 15W boards
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Patch Set 3:
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Patchset:
PS3:
PTAL
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Change subject: soc/amd/mendocino: Reinterpret smu_power_and_thm_limit
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Patch Set 4:
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