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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/acbbe1f3_f7d8cad1
PS11, Line 111: SPI_SOC_DI_FPMCU_DO_R
Why were these updated to `FPMCU`?
They are `TCHSCR` in go/myst-gpios.
The `FPMCU` GPIOs are below (140, 142).
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Change subject: mb/google/myst: Add new mainboard
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173329):
https://review.coreboot.org/c/coreboot/+/74093/comment/bccb660a_3b2c1653
PS8, Line 7: const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
need consistent spacing around '*' (ctx:WxO)
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Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74113
to look at the new patch set (#25).
Change subject: mb/google/myst: Configure WLAN
......................................................................
mb/google/myst: Configure WLAN
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mapping derived from myst schematic.
BUG=b:275965982
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/bootblock.c
A src/mainboard/google/myst/romstage.c
M src/mainboard/google/myst/variants/baseboard/Makefile.inc
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/gpio.c
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
7 files changed, 94 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/74113/25
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Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74111
to look at the new patch set (#24).
Change subject: mb/google/myst: Enable AP <-> GSC communication
......................................................................
mb/google/myst: Enable AP <-> GSC communication
Configure GSC I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for GSC device and enable the required
config items.
BUG=b:275959717
TEST=builds
Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/bootblock.c
M src/mainboard/google/myst/mainboard.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/gpio.c
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
6 files changed, 70 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/74111/24
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Add new mainboard
......................................................................
mb/google/myst: Add new mainboard
Myst is a new Google mainboard with an AMD Phoenix SOC.
BUG=b:270596106
TEST=util/abuild/abuild -t GOOGLE_MYST --clean
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a
---
A src/mainboard/google/myst/Kconfig
A src/mainboard/google/myst/Kconfig.name
A src/mainboard/google/myst/Makefile.inc
A src/mainboard/google/myst/board_info.txt
A src/mainboard/google/myst/bootblock.c
A src/mainboard/google/myst/chromeos.fmd
A src/mainboard/google/myst/dsdt.asl
A src/mainboard/google/myst/mainboard.c
A src/mainboard/google/myst/port_descriptors.c
A src/mainboard/google/myst/variants/baseboard/devicetree.cb
A src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
11 files changed, 188 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/74093/8
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 13: Code-Review+1
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Attention is currently required from: Jérémy Compostella.
Hello Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74205
to look at the new patch set (#3).
Change subject: soc/intel/cmn/cse: Fix unnecessary End-Of-Post cases
......................................................................
soc/intel/cmn/cse: Fix unnecessary End-Of-Post cases
This patch fixes commit e7a1204f26fe ("soc/intel/cmn/cse: Handle EOP
completion asynchronously").
Following the logic of `cse_send_eop()', there are two cases for which
End-Of-Post should not be performed:
1. CSE lite is in "soft temp disable" state and vboot is in recovery
mode
2. CSE is in "soft temp disable" state
This patch ensures that these two cases operate as expected. Even if
the "Esc-Refresh PowerButton" is used to enter recovery which lead to
a call of `do_send_end_of_post()' with CSE enabled (`is_cse_enable()'
returns true).
BUG:b/276927816
BRANCH=firmware-brya-14505.B
TEST=Enter recovery using "Esc-Refresh PowerButton" on brya/skolas
Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/common/block/cse/cse_eop.c
1 file changed, 38 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74205/3
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