Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74150 )
Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Makefile.inc: introduce all_x86 target
For compilation units that should be built for all stages that run on
the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP
which is an ARM core, the 'all' target can't be used, since that would
result in the compilation unit also being added to the verstage target
in the verstage on PSP case. In order to not need to add a compilation
unit to the 'bootblock', 'verstage_x86', 'romstage', and 'ramstage'
targets in separate lines in the Makefile, introduce the 'all_x86'
target that adds a file to 'bootblock', 'verstage_x86', 'romstage',
'postcar', and 'ramstage'. The compilation units also need to be added
to the 'postcar' stage which is only present on the pre-Zen SoCs to be
able to also use the 'all_x86' target in common AMD code that is also
used in those pre-Zen SoCs.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74150
Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
1 file changed, 31 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Fred Reitberger: Looks good to me, approved
Matt DeVillier: Looks good to me, approved
diff --git a/Makefile.inc b/Makefile.inc
index d2d3f88..6901ef4 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -107,6 +107,9 @@
$(call add-special-class,all)
all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
+$(call add-special-class,all_x86)
+all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
+
$(call add-special-class,verstage_x86)
ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
verstage_x86-handler = $(eval verstage-y += $(2))
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Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 )
Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
......................................................................
Patch Set 2: Code-Review+2
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Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
......................................................................
Patch Set 1: Code-Review+2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74099 )
Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 13:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173307):
https://review.coreboot.org/c/coreboot/+/74099/comment/c87d50db_238aef74
PS13, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173307):
https://review.coreboot.org/c/coreboot/+/74099/comment/add69a66_6380e32f
PS13, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74095
to look at the new patch set (#11).
Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
mb/google/myst: First pass GPIO configuration for Myst
Initial GPIO configuration for Myst.
BUG=b:270596581
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b
---
M src/mainboard/google/myst/variants/baseboard/gpio.c
1 file changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74095/11
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74206 )
Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74206/comment/4c52cf6b_b3827d36
PS1, Line 11: Revert initial change as it was causing a boot failure when transitioning
: into recovery mode.
> wrap up text?
Done
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Hello Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74206
to look at the new patch set (#2).
Change subject: Revert "mb/google/brya: Enable asynchronous End-Of-Post"
......................................................................
Revert "mb/google/brya: Enable asynchronous End-Of-Post"
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32.
Revert initial change as it was causing a boot failure when
transitioning into recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/Kconfig
M src/soc/intel/alderlake/Kconfig
2 files changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/74206/2
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Change subject: mb/google/myst: Enable variants for Myst
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/myst/Kconfig:
https://review.coreboot.org/c/coreboot/+/74098/comment/6070dae4_3b0d5773
PS11, Line 40: BOARD_GOOGLE_MYST
> I am not seeing Kconfig.name file with BOARD_GOOGLE_MYST configuration.
It was added in https://review.coreboot.org/c/coreboot/+/74093
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 10:
(7 comments)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/6c56aff9_5e67ee70
PS8, Line 79: * SPI_SOC_CLK_TCHSCR_R */
> SOC_CLK_FPMCU_R since all TS are I2C based for now. […]
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/4dcd24dc_25bde526
PS8, Line 83: /* SPI_SOC_CS_TCHSCR_R_L */
> Same comment as in line 79
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/18500a66_df59e631
PS8, Line 107: SSD
> WLAN
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/2125a0c3_2f128c18
PS8, Line 109: /* SPI_SOC_DO_TCHSCR_DI_R */
: PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE),
: /* SPI_SOC_DO_TCHSCR_DO_R */
: PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE)
> These are FPMCU only for now. Same comment as in line 79.
Should also get EE's to update schematic nets
https://review.coreboot.org/c/coreboot/+/74095/comment/064f7041_f127bcb8
PS8, Line 123: WLAN
> WWAN
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/cabd2ff9_4af5be00
PS8, Line 127:
> / SSD
Done
https://review.coreboot.org/c/coreboot/+/74095/comment/7ea6106c_645ee6f9
PS8, Line 142: PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
> Same comment as in line 79
Done
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Change subject: Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
......................................................................
Patch Set 1: Code-Review+2
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