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Change subject: mb/google/myst: Enable variants for Myst
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/myst/Kconfig:
https://review.coreboot.org/c/coreboot/+/74098/comment/3bc11fab_1297bbc2
PS11, Line 40: BOARD_GOOGLE_MYST
I am not seeing Kconfig.name file with BOARD_GOOGLE_MYST configuration.
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Change subject: mb/google/myst: First pass GPIO configuration for Myst
......................................................................
Patch Set 8:
(7 comments)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/920571b0_114c580d
PS8, Line 79: * SPI_SOC_CLK_TCHSCR_R */
SOC_CLK_FPMCU_R since all TS are I2C based for now.
Also these GPIOs should be configured with the NF only when SPI based FPMCU is used. A follow-up bug and a CL is required to address that.
https://review.coreboot.org/c/coreboot/+/74095/comment/34056706_a7fcdc55
PS8, Line 83: /* SPI_SOC_CS_TCHSCR_R_L */
Same comment as in line 79
https://review.coreboot.org/c/coreboot/+/74095/comment/9a0ec35f_d44e2317
PS8, Line 107: SSD
WLAN
https://review.coreboot.org/c/coreboot/+/74095/comment/0dcb8984_01b58e29
PS8, Line 109: /* SPI_SOC_DO_TCHSCR_DI_R */
: PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE),
: /* SPI_SOC_DO_TCHSCR_DO_R */
: PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE)
These are FPMCU only for now. Same comment as in line 79.
https://review.coreboot.org/c/coreboot/+/74095/comment/1c3c6544_3bca051d
PS8, Line 123: WLAN
WWAN
https://review.coreboot.org/c/coreboot/+/74095/comment/dc6b6cc8_cfef5156
PS8, Line 127:
/ SSD
https://review.coreboot.org/c/coreboot/+/74095/comment/f9d60f1e_0d05f883
PS8, Line 142: PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
Same comment as in line 79
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 12:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173278):
https://review.coreboot.org/c/coreboot/+/74099/comment/157f0d7c_3ba92964
PS12, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173278):
https://review.coreboot.org/c/coreboot/+/74099/comment/fb3597bb_0109d079
PS12, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Jon Murphy has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74107 )
Change subject: mb/google/myst: Log mainboard events to elog
......................................................................
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Change subject: mb/google/myst: Log mainboard events to elog
......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/smihandler.c:
https://review.coreboot.org/c/coreboot/+/74107/comment/45f16349_0d706ff6
PS5, Line 26: void elog_gsmi_cb_mainboard_log_wake_source(void)
> Was this supposed to be removed from this CL? […]
Yea, we should drop and abandon it.
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Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74099
to look at the new patch set (#12).
Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
mb/google/myst: Enable chromeOS EC
BUG=b:270624655
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: Id18a311097d575973087eb92fd446a5c511f570e
---
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/myst/Makefile.inc
M src/mainboard/google/myst/dsdt.asl
A src/mainboard/google/myst/ec.c
M src/mainboard/google/myst/mainboard.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
A src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h
7 files changed, 140 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/74099/12
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Change subject: mb/google/myst: Enable chromeOS EC
......................................................................
Patch Set 11:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/include/baseboard/ec.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173262):
https://review.coreboot.org/c/coreboot/+/74099/comment/ee7e0943_f0af91f5
PS11, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
space prohibited between function name and open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173262):
https://review.coreboot.org/c/coreboot/+/74099/comment/3fc85473_b72418bb
PS11, Line 71: #define SIO_EC_PS2K_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {1}
Macros with complex values should be enclosed in parentheses
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Change subject: mb/google/myst: Add new mainboard
......................................................................
Patch Set 7: Verified+1
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173256):
https://review.coreboot.org/c/coreboot/+/74093/comment/7a3b8e94_fa61c6a5
PS7, Line 7: const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
need consistent spacing around '*' (ctx:WxO)
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
mb/google/myst: Enable PCIe devices in devicetree
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/port_descriptors.c
M src/mainboard/google/myst/variants/baseboard/devicetree.cb
M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
3 files changed, 103 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74112/21
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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 20:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173254):
https://review.coreboot.org/c/coreboot/+/74112/comment/46470365_0cd32906
PS20, Line 8:
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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