coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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5739 discussions

[L] Change in coreboot[master]: mb/ibm: Add 4 SPR sockets server board IBM SBP1
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: David Hendricks, Angel Pons, Shuo Liu, Nill Ge. Hello build bot (Jenkins), Paul Menzel, David Hendricks, Angel Pons, Shuo Liu, Arthur Heymans, Nill Ge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73392 to look at the new patch set (#10). Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1 ...................................................................... mb/ibm: Add 4 SPR sockets server board IBM SBP1 The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs Test: The board boots to Linux 5.15 with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 --- A src/mainboard/ibm/Kconfig A src/mainboard/ibm/Kconfig.name A src/mainboard/ibm/sbp1/Kconfig A src/mainboard/ibm/sbp1/Kconfig.name A src/mainboard/ibm/sbp1/Makefile.inc A src/mainboard/ibm/sbp1/acpi/platform.asl A src/mainboard/ibm/sbp1/board.fmd A src/mainboard/ibm/sbp1/board_info.txt A src/mainboard/ibm/sbp1/bootblock.c A src/mainboard/ibm/sbp1/devicetree.cb A src/mainboard/ibm/sbp1/dsdt.asl A src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h A src/mainboard/ibm/sbp1/ramstage.c A src/mainboard/ibm/sbp1/romstage.c 14 files changed, 847 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73392/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Karthik Ramasubramanian (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Martin Roth, Fred Reitberger, Tim Van Patten, Felix Held, Mark Hasemeyer. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/648168f0_fc071c22 PS2, Line 2: SI_BIOS { > RECOVERY_MRC_CACHE should be 256K, same as the size of RW_MRC_CACHE […] Fred, Why is the MRC region increasing? I would like to understand since the memory technology is the same in both Skyrim and Myst. This has doubled between Guybrush and Skyrim. Now it has doubled again between Skyrim and Myst. File src/mainboard/google/myst/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/74093/comment/98f5644d_a1ce8925 PS3, Line 36: } > RO should cover the lowest flash offsets. See the birman `chromeos_phoenix. […] Given the lack of clarity on how things are looking for 32 MB SPI support, do you think we can address the comments for 16 MB layout and land that as a first pass. Once the required support has landed, we can add the 32 MB layout. -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 16:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add initial fch irq routing
by Tim Van Patten (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74109 ) Change subject: mb/google/myst: Add initial fch irq routing ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Gerrit-Change-Number: 74109 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 15:44:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
by Michał Żygowski (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Sumeet Pawnikar, Tarun Tuli, Subrata Banik, Michał Kopeć, Krystian Hebel, Vidya Gopalakrishnan. Hello Sumeet Pawnikar, build bot (Jenkins), Tarun Tuli, Subrata Banik, Michał Kopeć, Krystian Hebel, Vidya Gopalakrishnan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72998 to look at the new patch set (#2). Change subject: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current ...................................................................... soc/intel/alderlake/vr_config.c: Fix GT domain TDC current Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder Lake-S SKUs have GT TDC of 22A. Based on the default settings of ADL-S FSP. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 30 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/72998/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Gerrit-Change-Number: 72998 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Michał Żygowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#10). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 627 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 10 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
by Michał Żygowski (Code Review) 04 Apr '23

04 Apr '23

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[S] Change in coreboot[master]: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Michał Żygowski, Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68988 ) Change subject: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region ...................................................................... Patch Set 5: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd Gerrit-Change-Number: 68988 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 15:32:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
by Michał Żygowski (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Paul Menzel, Krystian Hebel. Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68987 to look at the new patch set (#5). Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash ...................................................................... soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f --- M Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/hsphy.c M util/cbfstool/default-x86.fmd 5 files changed, 313 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Gerrit-Change-Number: 68987 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
by Michał Żygowski (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Paul Menzel, Krystian Hebel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68987 ) Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68987/comment/57a18d7e_82840dcf PS3, Line 13: This change allows to : keep PCIe 5.0 functioning even if CSME/HECI is not functional. > Does it still work after adding or removing PCIe devices? It does not depend on the PCIe presence. Just the root port has to be enabled so that coreboot attempts to load the HSPHY File src/soc/intel/alderlake/hsphy.c: https://review.coreboot.org/c/coreboot/+/68987/comment/383efcfd_dd14b829 PS3, Line 222: printk(BIOS_ERR, "Invalid parameters, HSPHY will not be cached in flash.\n"); > I think this misses a return. Indeed, fixed. https://review.coreboot.org/c/coreboot/+/68987/comment/69e8d5d1_3aea736b PS3, Line 233: if (hsphy_cache_valid(hsphy_fw_cache)) { > Update is skipped if content of `buf` is different than cached version, is this the expected behavio […] I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if needed. Also laoding from cache is attempted if any fail in the normal flow occurs. https://review.coreboot.org/c/coreboot/+/68987/comment/fb525154_858a9745 PS3, Line 234: printk(BIOS_INFO, "HSPHY: HSPHY cache valid, skipping update\n"); > How can this happen? In line 313 the firmware is loaded from cache, isn’t it. […] Indeed, Krystian also pointed it out. I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if needed. Also laoding from cache is attempted if any fail in the normal flow occurs. https://review.coreboot.org/c/coreboot/+/68987/comment/794f2cc2_4e002440 PS3, Line 240: printk(BIOS_ERR, "HSPHY: HSPHY_FW region too small\n"); > Please also log the size values. Done https://review.coreboot.org/c/coreboot/+/68987/comment/12030b22_f4c44399 PS3, Line 246: hsphy_fw_cache = malloc(sizeof(*hsphy_fw_cache)); > No `rdev_munmap` before `hsphy_fw_cache` is overwritten. Yup, fixed https://review.coreboot.org/c/coreboot/+/68987/comment/ed3a6bc4_dd173636 PS3, Line 314: return; > I’d log the successful loading in this location. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Gerrit-Change-Number: 68987 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 15:29:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Michał Kopeć. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68988 ) Change subject: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region ...................................................................... Patch Set 4: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd Gerrit-Change-Number: 68988 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 15:19:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023