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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 4:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68987/comment/57a18d7e_82840dcf
PS3, Line 13: This change allows to
: keep PCIe 5.0 functioning even if CSME/HECI is not functional.
> Does it still work after adding or removing PCIe devices?
It does not depend on the PCIe presence. Just the root port has to be enabled so that coreboot attempts to load the HSPHY
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/383efcfd_dd14b829
PS3, Line 222: printk(BIOS_ERR, "Invalid parameters, HSPHY will not be cached in flash.\n");
> I think this misses a return.
Indeed, fixed.
https://review.coreboot.org/c/coreboot/+/68987/comment/69e8d5d1_3aea736b
PS3, Line 233: if (hsphy_cache_valid(hsphy_fw_cache)) {
> Update is skipped if content of `buf` is different than cached version, is this the expected behavio […]
I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if needed. Also laoding from cache is attempted if any fail in the normal flow occurs.
https://review.coreboot.org/c/coreboot/+/68987/comment/fb525154_858a9745
PS3, Line 234: printk(BIOS_INFO, "HSPHY: HSPHY cache valid, skipping update\n");
> How can this happen? In line 313 the firmware is loaded from cache, isn’t it. […]
Indeed, Krystian also pointed it out. I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if needed. Also laoding from cache is attempted if any fail in the normal flow occurs.
https://review.coreboot.org/c/coreboot/+/68987/comment/794f2cc2_4e002440
PS3, Line 240: printk(BIOS_ERR, "HSPHY: HSPHY_FW region too small\n");
> Please also log the size values.
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/12030b22_f4c44399
PS3, Line 246: hsphy_fw_cache = malloc(sizeof(*hsphy_fw_cache));
> No `rdev_munmap` before `hsphy_fw_cache` is overwritten.
Yup, fixed
https://review.coreboot.org/c/coreboot/+/68987/comment/ed3a6bc4_dd173636
PS3, Line 314: return;
> I’d log the successful loading in this location.
Done
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Change subject: mainboard/msi/ms7d25/vboot-rwab.fmd: Add HSPHY cache region
......................................................................
Patch Set 4: Verified+1
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Hello build bot (Jenkins), Tarun Tuli, Martin L Roth, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68987
to look at the new patch set (#4).
Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
Tge patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 functioning even if CSME/HECI is not functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
---
M Makefile.inc
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/hsphy.c
M util/cbfstool/default-x86.fmd
5 files changed, 313 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/68987/4
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Change subject: payloads/external/edk2: Add option to clone edk2-platforms repo
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/starlabs/starbook: Disable ASPM in coreboot
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73982/comment/c13759c2_ef6b4294
PS4, Line 7: ASPM
Should have been “ASPM configuration”. ;-)
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Change subject: payloads/external/edk2: Add option to clone edk2-platforms repo
......................................................................
Patch Set 4:
(1 comment)
File payloads/external/edk2/Makefile:
https://review.coreboot.org/c/coreboot/+/68872/comment/8cd8fe68_c96f9cd4
PS4, Line 146: clean
> By specifying full message ("nothing to commit, working tree clean") you would be safer against poss […]
Done
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I'd like you to reexamine a change. Please visit
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Change subject: payloads/external/edk2: Add option to clone edk2-platforms repo
......................................................................
payloads/external/edk2: Add option to clone edk2-platforms repo
Add possibility to clone edk2-platforms repository. Some edk2
repositories may use modules from edk2-platforms which contains
various feature packages for Intel platforms, e.g VT-d driver if DMA
protection is enabled.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: Iabd0793dfdcb95260046dc992ff30ef581159db9
---
M payloads/external/Makefile.inc
M payloads/external/edk2/Kconfig
M payloads/external/edk2/Makefile
3 files changed, 76 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/68872/5
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Change subject: mb/ibm: Add IBM SBP1
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/ibm/sbp1/Kconfig:
https://review.coreboot.org/c/coreboot/+/73392/comment/d9d4cc64_031b4146
PS9, Line 31: MAX_SOCKET_UPD
> Help text says: […]
I don't understand the question.
It must be increased to support 4 sockets.
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Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block
......................................................................
Patch Set 15:
(4 comments)
File src/soc/intel/common/block/oc_wdt/Kconfig:
https://review.coreboot.org/c/coreboot/+/68944/comment/a3117689_9d246506
PS15, Line 8: chipset
> overclocking
Done
https://review.coreboot.org/c/coreboot/+/68944/comment/a3de47f3_dd5180ce
PS15, Line 18: Watchdog
> Overclocking watchdog
Done
File src/soc/intel/common/block/smm/smihandler.c:
https://review.coreboot.org/c/coreboot/+/68944/comment/6c865b0e_d9c863b9
PS15, Line 215: pmc_clear_pm1_status();
> Yeah, have to get rid of that.
Done
File src/soc/intel/common/block/smm/smm.c:
https://review.coreboot.org/c/coreboot/+/68944/comment/82c73aff_1cfdce09
PS15, Line 45: Also we do not allow timeouts lower than 60s
> Forced by Kconfig range definition
Added it to the comment.
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