April 2023 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Michał Żygowski (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Nico Huber, Martin L Roth, Benjamin Doron, Michał Kopeć, Angel Pons, Maximilian Brune, Arthur Heymans, Werner Zeh. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944 ) Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... Patch Set 15: (4 comments) File src/soc/intel/common/block/oc_wdt/Kconfig: https://review.coreboot.org/c/coreboot/+/68944/comment/a3117689_9d246506 PS15, Line 8: chipset > overclocking Done https://review.coreboot.org/c/coreboot/+/68944/comment/a3de47f3_dd5180ce PS15, Line 18: Watchdog > Overclocking watchdog Done File src/soc/intel/common/block/smm/smihandler.c: https://review.coreboot.org/c/coreboot/+/68944/comment/6c865b0e_d9c863b9 PS15, Line 215: pmc_clear_pm1_status(); > Yeah, have to get rid of that. Done File src/soc/intel/common/block/smm/smm.c: https://review.coreboot.org/c/coreboot/+/68944/comment/82c73aff_1cfdce09 PS15, Line 45: Also we do not allow timeouts lower than 60s > Forced by Kconfig range definition Added it to the comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/68944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 14:12:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/starlabs/*: Add CMOS entries for the mirror flag
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73682 ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/*: Add CMOS entries for the mirror flag ...................................................................... mb/starlabs/*: Add CMOS entries for the mirror flag Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/lite/cmos.default M src/mainboard/starlabs/lite/cmos.layout M src/mainboard/starlabs/lite/variants/glkr/cmos.default M src/mainboard/starlabs/lite/variants/glkr/cmos.layout M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/tgl/cmos.default M src/mainboard/starlabs/starbook/variants/tgl/cmos.layout 8 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/lite/cmos.default b/src/mainboard/starlabs/lite/cmos.default index 2455e2b..c59bbe5 100644 --- a/src/mainboard/starlabs/lite/cmos.default +++ b/src/mainboard/starlabs/lite/cmos.default @@ -12,6 +12,7 @@ # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable +mirror_flag=Disable # southbridge power_on_after_fail=Disable # Functions diff --git a/src/mainboard/starlabs/lite/cmos.layout b/src/mainboard/starlabs/lite/cmos.layout index e6b3be2..71dd390 100644 --- a/src/mainboard/starlabs/lite/cmos.layout +++ b/src/mainboard/starlabs/lite/cmos.layout @@ -28,6 +28,8 @@ # coreboot config options: EC 600 3 e 4 kbl_timeout 608 1 e 1 fn_ctrl_swap +616 1 e 1 mirror_flag +624 4 h 0 mirror_flag_counter # coreboot config options: southbridge 800 2 e 6 power_on_after_fail diff --git a/src/mainboard/starlabs/lite/variants/glkr/cmos.default b/src/mainboard/starlabs/lite/variants/glkr/cmos.default index dedd7f7..3dbe92d 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/cmos.default +++ b/src/mainboard/starlabs/lite/variants/glkr/cmos.default @@ -13,6 +13,7 @@ kbl_timeout=30 seconds fn_ctrl_swap=Disable fast_charge=Normal +mirror_flag=Disable # southbridge power_on_after_fail=Disable # Functions diff --git a/src/mainboard/starlabs/lite/variants/glkr/cmos.layout b/src/mainboard/starlabs/lite/variants/glkr/cmos.layout index 3dfc8de..d53116c 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/cmos.layout +++ b/src/mainboard/starlabs/lite/variants/glkr/cmos.layout @@ -29,6 +29,8 @@ 600 3 e 4 kbl_timeout 608 1 e 1 fn_ctrl_swap 616 1 e 11 fast_charge +624 1 e 1 mirror_flag +632 4 h 0 mirror_flag_counter # coreboot config options: southbridge 800 2 e 6 power_on_after_fail diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default index 151686c..18abc93 100644 --- a/src/mainboard/starlabs/starbook/cmos.default +++ b/src/mainboard/starlabs/starbook/cmos.default @@ -16,6 +16,7 @@ # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable +mirror_flag=Disable # southbridge power_on_after_fail=Disable # Functions diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index 9fc0b7d..fa912b5 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -35,6 +35,8 @@ 608 1 e 1 fn_ctrl_swap 616 2 e 8 max_charge 624 2 e 9 fan_mode +632 1 e 1 mirror_flag +640 4 h 0 mirror_flag_counter # coreboot config options: southbridge 800 2 e 6 power_on_after_fail diff --git a/src/mainboard/starlabs/starbook/variants/tgl/cmos.default b/src/mainboard/starlabs/starbook/variants/tgl/cmos.default index cfc9a61..cca64fe 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/cmos.default +++ b/src/mainboard/starlabs/starbook/variants/tgl/cmos.default @@ -16,6 +16,7 @@ # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable +mirror_flag=Disable # southbridge power_on_after_fail=Disable # Functions diff --git a/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout b/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout index c4a49c5d..1700d0d 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout +++ b/src/mainboard/starlabs/starbook/variants/tgl/cmos.layout @@ -35,6 +35,8 @@ 608 1 e 1 fn_ctrl_swap 616 2 e 8 max_charge 624 2 e 9 fan_mode +632 1 e 1 mirror_flag +640 4 h 0 mirror_flag_counter # coreboot config options: southbridge 800 2 e 6 power_on_after_fail -- To view, visit https://review.coreboot.org/c/coreboot/+/73682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Gerrit-Change-Number: 73682 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Michał Żygowski (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Nico Huber, Martin L Roth, Benjamin Doron, Michał Kopeć, Angel Pons, Maximilian Brune, Arthur Heymans, Werner Zeh. Hello build bot (Jenkins), Nico Huber, Benjamin Doron, Paul Menzel, Michał Kopeć, Maximilian Brune, Angel Pons, Arthur Heymans, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68944 to look at the new patch set (#16). Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... soc/intel/common/block/oc_wdt: Add OC watchdog common block Add new block for handling overcloking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the microarchitectures utilizing intelblocks. The patch adds the common block for initializing and feeding the watchdog. Timeout is configurable via Kconfig and cannot be set to less than 60 seconds to avoid reset loops when full memory training is needed. The patch also adds support for feeding watchdog in driverless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc --- A src/soc/intel/common/block/include/intelblocks/oc_wdt.h A src/soc/intel/common/block/oc_wdt/Kconfig A src/soc/intel/common/block/oc_wdt/Makefile.inc A src/soc/intel/common/block/oc_wdt/oc_wdt.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smm.c 6 files changed, 187 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/68944/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/68944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: ec/starlabs/merlin: Add support for the ITE mirror flag
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73044 ) Change subject: ec/starlabs/merlin: Add support for the ITE mirror flag ...................................................................... ec/starlabs/merlin: Add support for the ITE mirror flag When enabled, the EC will mirror the firmware contained inside the coreboot ROM. This allows it to be updated at the same time as coreboot. Enable the mirror flag if the installed EC firmware does not match the target version or if a CMOS option, "manual_mirror_flag" is set. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/variants/adl/ecdefs.h M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/cml/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/ec/starlabs/merlin/variants/tgl/ecdefs.h 12 files changed, 114 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig index 6ccd217..5939854 100644 --- a/src/ec/starlabs/merlin/Kconfig +++ b/src/ec/starlabs/merlin/Kconfig @@ -64,6 +64,20 @@ help Select if the mainboard supports limiting the maximum charge of the battery. +config EC_STARLABS_MIRROR_SUPPORT + bool "Enable mirror flag support" + default n + depends on EC_STARLABS_ITE + help + Select if the EC should mirror the EC firmware contained in the coreboot ROM. + +config EC_STARLABS_MIRROR_VERSION + hex "Version of the EC firmware that should be installed." + depends on EC_STARLABS_MIRROR_SUPPORT + help + The version of the EC that should be installed. The mirror flag will be activated + if this Kconfig option is set and it does not match the current EC version. + config EC_STARLABS_MERLIN bool "Use open-source Merlin EC Firmware" default n diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index ca1d081..2fe5ec5 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -98,6 +98,13 @@ #define KBL_DISABLED 0x00 #define KBL_ENABLED 0xdd +/* Mirror Flag */ +#define MIRROR_DISABLED 0x00 +#define MIRROR_ENABLED 0xaa + +#define MIRROR_ATTEMPTS 1 + uint16_t ec_get_version(void); +void ec_mirror_flag(void); #endif diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 357c67c..9730647 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -6,6 +6,7 @@ #include <ec/acpi/ec.h> #include <option.h> #include <pc80/keyboard.h> +#include <halt.h> #include "ec.h" #include "ecdefs.h" @@ -26,6 +27,66 @@ return lut[index]; } +static void ec_mirror_with_count(void) +{ + unsigned int cmos_mirror_flag_counter = get_uint_option("mirror_flag_counter", UINT_MAX); + + if (cmos_mirror_flag_counter != UINT_MAX) { + printk(BIOS_DEBUG, "ITE: mirror_flag_counter = %u\n", cmos_mirror_flag_counter); + + /* Avoid boot loops by only trying a state change once */ + if (cmos_mirror_flag_counter < MIRROR_ATTEMPTS) { + cmos_mirror_flag_counter++; + set_uint_option("mirror_flag_counter", cmos_mirror_flag_counter); + printk(BIOS_DEBUG, "ITE: Mirror attempt %u/%u.\n", cmos_mirror_flag_counter, + MIRROR_ATTEMPTS); + + /* Write the EC mirror flag */ + ec_write(ECRAM_MIRROR_FLAG, MIRROR_ENABLED); + + /* Check what has been written */ + if (ec_read(ECRAM_MIRROR_FLAG) == MIRROR_ENABLED) + poweroff(); + } else { + /* + * If the mirror flags fails after 1 attempt, it will + * likely need a cold boot, or recovering. + */ + printk(BIOS_ERR, "ITE: Failed to mirror the EC in %u attempts!\n", + MIRROR_ATTEMPTS); + } + } else { + printk(BIOS_DEBUG, "ITE: Powering Off"); + /* Write the EC mirror flag */ + ec_write(ECRAM_MIRROR_FLAG, MIRROR_ENABLED); + + /* Check what has been written */ + if (ec_read(ECRAM_MIRROR_FLAG) == MIRROR_ENABLED) + poweroff(); + } +} + + +void ec_mirror_flag(void) +{ + /* + * For the mirror flag to work, the status of the EC pin must be known + * at all times, which means external power. This can be either a DC + * charger, or PD with CCG6. PD with an ANX7447 requires configuration + * from the EC, so the update will interrupt this. + * + * This means we can unconditionally apply the mirror flag to devices + * that have CCG6, present on devices with TBT, but have a manual + * flag for devices without it. + */ + if (CONFIG(EC_STARLABS_MIRROR_SUPPORT) && + (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS) || get_uint_option("mirror_flag", 0)) && + (ec_get_version() != CONFIG_EC_STARLABS_MIRROR_VERSION)) { + printk(BIOS_ERR, "ITE: System and EC ROM version mismatch.\n"); + ec_mirror_with_count(); + } +} + static uint16_t ec_get_chip_id(unsigned int port) { return (pnp_read_index(port, ITE_CHIPID1) << 8) | @@ -57,6 +118,8 @@ return; } + ec_mirror_flag(); + pc_keyboard_init(NO_AUX_DEVICE); /* diff --git a/src/ec/starlabs/merlin/variants/adl/ecdefs.h b/src/ec/starlabs/merlin/variants/adl/ecdefs.h index 28f7e4b..f7c584c 100644 --- a/src/ec/starlabs/merlin/variants/adl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/adl/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE 0x1a #define ECRAM_FAN_MODE 0x1b #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x05 #endif diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h index fa7e79b..5cbe14e 100644 --- a/src/ec/starlabs/merlin/variants/apl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h index 6942c39..0c522cc 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_KBL_BRIGHTNESS 0x36 #define ECRAM_FN_LOCK_STATE 0x70 #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x05 #endif diff --git a/src/ec/starlabs/merlin/variants/cml/ecdefs.h b/src/ec/starlabs/merlin/variants/cml/ecdefs.h index 6a24bc4..0a2654b 100644 --- a/src/ec/starlabs/merlin/variants/cml/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cml/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_KBL_BRIGHTNESS 0x19 #define ECRAM_FN_LOCK_STATE 0x2c #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index fefdd14..b2e2f2f 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index 038c378..ecc117c 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE 0x18 +#define ECRAM_MIRROR_FLAG dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index 3b69317..8f3355d 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_FN_CTRL_REVERSE 0x43 #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index f02c73a..08f80cb 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -20,5 +20,6 @@ #define ECRAM_FAN_MODE 0x50 #define ECRAM_MAX_CHARGE 0x51 #define ECRAM_FAST_CHARGE 0x52 +#define ECRAM_MIRROR_FLAG 0x05 #endif diff --git a/src/ec/starlabs/merlin/variants/tgl/ecdefs.h b/src/ec/starlabs/merlin/variants/tgl/ecdefs.h index cbc7b86e..c17b025 100644 --- a/src/ec/starlabs/merlin/variants/tgl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/tgl/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE 0x1a #define ECRAM_FAN_MODE 0x1b #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_MIRROR_FLAG 0x05 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/73044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I377abbb37dc4d3e535e518a73e73969b25967daa Gerrit-Change-Number: 73044 Gerrit-PatchSet: 26 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Add an option to enable Hot Plug
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73092 ) Change subject: mb/starlabs/starbook/adl: Add an option to enable Hot Plug ...................................................................... mb/starlabs/starbook/adl: Add an option to enable Hot Plug Some third-party SSDs, from Samsung and WD, such as the 990 Pro and WD Black 850X aren't initialised by coreboot, seemingly as coreboot is too quick; debug builds work, and enabling hotplug does. Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these SSDs to work. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/adl/Makefile.inc A src/mainboard/starlabs/starbook/variants/adl/ramstage.c 4 files changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default index f1276cc..151686c 100644 --- a/src/mainboard/starlabs/starbook/cmos.default +++ b/src/mainboard/starlabs/starbook/cmos.default @@ -12,6 +12,7 @@ webcam=Enable microphone=Enable legacy_8254_timer=Disable +pci_hot_plug=Disable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index 887c0b2..9fc0b7d 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -28,6 +28,7 @@ 512 1 e 1 webcam 520 1 e 1 microphone 528 1 e 1 legacy_8254_timer +536 1 e 1 pci_hot_plug # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc b/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc index 2a505c3..9abc069 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc +++ b/src/mainboard/starlabs/starbook/variants/adl/Makefile.inc @@ -7,3 +7,4 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c new file mode 100644 index 0000000..7accb1d --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/ramstage.h> + + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * Enable Hot Plug on RP5 to slow down coreboot so that + * third-party drives are detected. + */ + if (get_uint_option("pci_hot_plug", 0) == 1) + supd->PcieRpHotPlug[4] = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Gerrit-Change-Number: 73092 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/starlabs/starbook: Disable ASPM in coreboot
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73982 ) Change subject: mb/starlabs/starbook: Disable ASPM in coreboot ...................................................................... mb/starlabs/starbook: Disable ASPM in coreboot ASPM is already configured by FSP so disable it in coreboot to reduce boot time by a whopping 34ms. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/starlabs/starbook/Kconfig 1 file changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jakub Czapiga: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index d35a4d2..b2dfe12 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -145,9 +145,30 @@ string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" +config PCIEXP_ASPM + bool + default n + help + FSP is already taking care of ASPM, which is configured through the devicetree in coreboot + on Alderlake Platforms. Disable it to save some boot time. + config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS default 32 +config PCIEXP_L1_SUB_STATE + bool + default n + help + Enabling PCIe L1 sub states is already done in FSP. + Disable it to save some boot time. + +config PCIEXP_CLK_PM + bool + default n + help + Enabling PCIe clock power management is already done in FSP. + Disable it to save some boot time + config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL -- To view, visit https://review.coreboot.org/c/coreboot/+/73982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Gerrit-Change-Number: 73982 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/apollolake/include/soc/pmc.h: Add file
by Michał Żygowski (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69900 ) Change subject: soc/intel/apollolake/include/soc/pmc.h: Add file ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69900/comment/f91b28b4_5c7aafc7 PS5, Line 10: pm.h > Why not rename this file? I was thinking about it, but when I saw what other SoCs include in the pm.h and pmc.h and that it is not always consistent, I hesitated to rename it. The overlap of pm.h and pmc.h is not quite clear to me. Furthermore, renaming could cause many unwanted side effects that could easily miss my attention accidentally due to too many changes involved. Let me know WDYT -- To view, visit https://review.coreboot.org/c/coreboot/+/69900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c Gerrit-Change-Number: 69900 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 14:07:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: src/commonlib/fsp_relocate.c: Fixed NULL pointer dereferencing nparse...
by build bot (Jenkins) (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74204 ) Change subject: src/commonlib/fsp_relocate.c: Fixed NULL pointer dereferencing nparsed need not pass NULL for offsets other than 0. fih_offset is set only when the value stored in it is 0. Hence no need to pass a NULL pointer to indicate the offset is 0. ...................................................................... Patch Set 1: (5 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173187): https://review.coreboot.org/c/coreboot/+/74204/comment/b758f76b_d838620b PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173187): https://review.coreboot.org/c/coreboot/+/74204/comment/f878a6fe_fbdd8213 PS1, Line 12: Must return when fsp_version_cbmem is NULL, else the pointer is dereferenced Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173187): https://review.coreboot.org/c/coreboot/+/74204/comment/b2ada1df_e02ca7ad PS1, Line 15: usb4_path must be freed before exiting the fucntion as it is not used elsewhere Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173187): https://review.coreboot.org/c/coreboot/+/74204/comment/a9188090_aa0d5a09 PS1, Line 15: usb4_path must be freed before exiting the fucntion as it is not used elsewhere 'fucntion' may be misspelled - perhaps 'function'? File src/drivers/intel/fsp2_0/memory_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173187): https://review.coreboot.org/c/coreboot/+/74204/comment/81252afa_36857da3 PS1, Line 59: if (!fsp_version_cbmem){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/c/coreboot/+/74204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd54cc810b31c5bf3fb856078c548a5e6f44dcf9 Gerrit-Change-Number: 74204 Gerrit-PatchSet: 1 Gerrit-Owner: Shivani Joshi Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:52:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: acpigen_usb.c: Fixed memory leak The fresh variable malloced, freed a...
by build bot (Jenkins) (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74203 ) Change subject: acpigen_usb.c: Fixed memory leak The fresh variable malloced, freed after use ...................................................................... Patch Set 1: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173186): https://review.coreboot.org/c/coreboot/+/74203/comment/1d13a765_5eb8f747 PS1, Line 16: string.c: NULL pointer dereferenced Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/lib/string.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173186): https://review.coreboot.org/c/coreboot/+/74203/comment/79bfa8d3_c20628b2 PS1, Line 182: if (str == NULL){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173186): https://review.coreboot.org/c/coreboot/+/74203/comment/0b51933f_1df82a80 PS1, Line 183: if (ptr == NULL){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173186): https://review.coreboot.org/c/coreboot/+/74203/comment/fe833d18_521e035d PS1, Line 183: if (ptr == NULL){ braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/74203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07de77e80957a2439f1fc0ab992345456c887c9c Gerrit-Change-Number: 74203 Gerrit-PatchSet: 1 Gerrit-Owner: Shivani Joshi Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:52:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Stefan Ott, Alexander Couzens. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 7 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:49:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0