April 2023 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Jason Glenesk, ritul guru, Anand Vaikar, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74075 to look at the new patch set (#5). Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence update the correct bridge number in the device tree. TEST: Builds and boots, the device enumerates. [DEBUG] PCI: 00:02.4 [1022/14ee] enabled [DEBUG] PCI: 01:00.0 [144d/a80a] enabled Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74075/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 5 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Remove Soundwire workaround
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72669 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl: Remove Soundwire workaround ...................................................................... mb/starlabs/starbook/adl: Remove Soundwire workaround This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/acpi/mainboard.asl 1 file changed, 17 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/acpi/mainboard.asl b/src/mainboard/starlabs/starbook/acpi/mainboard.asl index 5bdde36..34b90af 100644 --- a/src/mainboard/starlabs/starbook/acpi/mainboard.asl +++ b/src/mainboard/starlabs/starbook/acpi/mainboard.asl @@ -3,32 +3,3 @@ Scope (\_SB) { #include "sleep.asl" } - -/* - * This platform doesn't support SoundWire but there - * is a kernel bug in some 5.10.x releases. - * - * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More - * details can be found at https://bit.ly/3ttdffG but it appears to - * be triggered by missing SoundWire ACPI entries. - * - * Add the minimal set to make it work again. - */ -Scope (_SB.PCI0.HDAS) -{ - Device (SNDW) - { - Name (_ADR, 0x40000000) - - Name (_CID, Package (0x02) - { - "PRP0001", - "PNP0A05" - }) - - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Gerrit-Change-Number: 72669 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/omnigul: Add ADL and RPL dptf settings
by Felix Held (Code Review) April 4, 2023

April 4, 2023

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73945 ) Change subject: mb/google/brya/var/omnigul: Add ADL and RPL dptf settings ...................................................................... mb/google/brya/var/omnigul: Add ADL and RPL dptf settings Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul BUG=b:273415170 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/omnigul/Makefile.inc M src/mainboard/google/brya/variants/omnigul/overridetree.cb A src/mainboard/google/brya/variants/omnigul/ramstage.c 3 files changed, 149 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Subrata Banik: Looks good to me, approved Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/omnigul/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/Makefile.inc index 8843e0d..810ceb2 100644 --- a/src/mainboard/google/brya/variants/omnigul/Makefile.inc +++ b/src/mainboard/google/brya/variants/omnigul/Makefile.inc @@ -5,6 +5,8 @@ ramstage-y += variant.c +ramstage-y += ramstage.c + romstage-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index 00e4eec..2af7db4 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -82,7 +82,115 @@ # Enable the Cnvi BT Audio Offload register "cnvi_bt_audio_offload" = "1" + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 55, + .tdp_pl4 = 123, + }" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + + register "tcc_offset" = "8" + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 100), + TEMP_PCT(52, 46), + TEMP_PCT(46, 40), + TEMP_PCT(41, 35), + TEMP_PCT(40, 28), + TEMP_PCT(34, 26), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 46), + TEMP_PCT(49, 40), + TEMP_PCT(45, 35), + TEMP_PCT(40, 28), + TEMP_PCT(35, 26), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end device ref i2c0 on chip drivers/i2c/generic register "hid" = ""RTL5682"" diff --git a/src/mainboard/google/brya/variants/omnigul/ramstage.c b/src/mainboard/google/brya/variants/omnigul/ramstage.c new file mode 100644 index 0000000..a208875 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DID_INTEL_ADL_P_ID_7, 15, 15000, 25000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 15000, 25000, 55000, 55000, 123000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 15000, 25000, 55000, 55000, 114000 }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, 15000, 25000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Gerrit-Change-Number: 73945 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Arthur Heymans (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Arthur Heymans, Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Christian Walter, Angel Pons, Shuming Chu (Shuming), TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 29: (1 comment) File src/soc/intel/xeon_sp/nb_acpi.c: https://review.coreboot.org/c/coreboot/+/68912/comment/5af30305_e6f30b72 PS24, Line 29: uint32_t > Could this be `unsigned int`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 29 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 04 Apr 2023 12:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Arthur Heymans (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Arthur Heymans, Lance Zhao, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Christian Walter, Angel Pons, Shuming Chu (Shuming), TangYiwei. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 28: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68912/comment/a95b324d_f2b473fd PS24, Line 13: it's > its Done https://review.coreboot.org/c/coreboot/+/68912/comment/9ab8aaf2_3d296d0f PS24, Line 16: entry (now it is done in : parallel too as a bonus). > Please add the dot/period after entry, and make the sentence in the brackets start with capital lett […] Done https://review.coreboot.org/c/coreboot/+/68912/comment/f7f2b4a0_373094d6 PS24, Line 18: > Tested on what board? Previous patches were tested on ocp/deltalake. current patchset is untested. -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 28 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 04 Apr 2023 12:31:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Arthur Heymans (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Lance Zhao, Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Angel Pons, Shuming Chu (Shuming), TangYiwei. Hello Lance Zhao, build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Wawrzynczak, Christian Walter, Angel Pons, TangYiwei, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68912 to look at the new patch set (#29). Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... soc/intel/xeon_sp: Don't sort struct device cpus for numa Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c 5 files changed, 59 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/68912/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 29 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Stefan Ott, Alexander Couzens. Bill XIE has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Removed Code-Review+2 by Bill XIE <persmule(a)hardenedlinux.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 7 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: deleteVote

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Stefan Ott, Alexander Couzens. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 7 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 04 Apr 2023 12:25:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Karol Zmyslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 9: (11 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/73934/comment/ad89fe62_55d54a03 PS4, Line 11: Document Number: 618876 > @Karol, please change it to refer to Datasheet Vol 2, as it seems to contain the necessary informati […] Corrected, in current commit (Patchset #9) Patchset: PS9: Respond to comments. File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/df7a0916_7942c956 PS4, Line 141: "L_BLKTEN", : "L_BLKTCTL", : "LVDDEN", : "SYS_PWROK", : "SYS_RESETB", : "MLK_RSTB", > What NF1 stands for? Corrected, in Patchset #8 https://review.coreboot.org/c/coreboot/+/73934/comment/03fdf5f1_0955318f PS4, Line 191: "JTAG_TD0", : "JTAGX", : "PRDYB", : "PREQB", : "CPU_TRSTB", : "JTAG_TDI", : "JTAG_TMS", : "JTAG_TCK", : "ITP_PMODE" > Same here, copy as NF1 and increase func_count Corrected, in patchset #8 https://review.coreboot.org/c/coreboot/+/73934/comment/c2451d42_0dd4fb24 PS4, Line 281: "GSPI2_CLK_LOOPBK", : "SPI1_CLK_LOOPBK", > Other microarchitectures incoporate the clock loopbacks to the previous GPIO group. […] Corrected, in patchset #9. https://review.coreboot.org/c/coreboot/+/73934/comment/9c95e8a7_8987da95 PS4, Line 312: "GSPI0_CLK_LOOPBK", : "GSPI1_CLK_LOOPBK", > Other microarchitectures incoporate the clock loopbacks to the previous GPIO group. […] Corrected, in patchset #9. https://review.coreboot.org/c/coreboot/+/73934/comment/f4965dfa_3ccd5c1c PS4, Line 336: .pad_count = ARRAY_SIZE(jasperlake_pch_group_r_names) / 6, : .func_count = 6, > There are only 3 columns not 6 Corrected. https://review.coreboot.org/c/coreboot/+/73934/comment/48da3a33_26ce305e PS4, Line 354: .pad_count = ARRAY_SIZE(jasperlake_pch_group_s_names) / 2, : .func_count = 2, > Ack Corrected. https://review.coreboot.org/c/coreboot/+/73934/comment/516f63e8_0b926966 PS4, Line 361: "HDACPU_SDI", : "HDACPU_SDO", : "HDACPU_SCLK", : "PM_SYNC", : "PECI", : "CPUPWRGD", : "THRMTRIPB", : "PLTRST_CPUB", : "PM_DOWN", : "TRIGGER_IN", : "TRIGGER_OUT", : "UFS_RESETB", : "CLKOUT_CPURTC", : "VCCST_PWRGD", : "C10_WAKE", > Ack Corrected. https://review.coreboot.org/c/coreboot/+/73934/comment/89b23c29_f205cd87 PS4, Line 386: "VGPIO_PCIE0", : "VGPIO_PCIE1", : "VGPIO_PCIE2", : "VGPIO_PCIE3", : "VGPIO_PCIE4", : "VGPIO_PCIE5", : "VGPIO_PCIE6", : "VGPIO_PCIE7", : "VGPIO_PCIE8", : "VGPIO_PCIE9", : "VGPIO_PCIE10", : "VGPIO_PCIE11", : "VGPIO_PCIE12", : "VGPIO_PCIE13", : "VGPIO_PCIE14", : "VGPIO_PCIE15", : "VGPIO_PCIE16", : "VGPIO_PCIE17", : "VGPIO_PCIE18", : "VGPIO_PCIE19", : "VGPIO_PCIE20", : "VGPIO_PCIE21", : "VGPIO_PCIE22", : "VGPIO_PCIE23", : "VGPIO_PCIE24", : "VGPIO_PCIE25", : "VGPIO_PCIE26", : "VGPIO_PCIE27", : "VGPIO_PCIE28", : "VGPIO_PCIE29", : "VGPIO_PCIE30", : "VGPIO_PCIE31", : "VGPIO_PCIE32", : "VGPIO_PCIE33", : "VGPIO_PCIE34", : "VGPIO_PCIE35", : "VGPIO_PCIE36", : "VGPIO_PCIE37", : "VGPIO_PCIE38", : "VGPIO_PCIE39", : "VGPIO_PCIE40", : "VGPIO_PCIE41", : "VGPIO_PCIE42", : "VGPIO_PCIE43", : "VGPIO_PCIE44", : "VGPIO_PCIE45", : "VGPIO_PCIE46", : "VGPIO_PCIE47", : "VGPIO_PCIE48", : "VGPIO_PCIE49", : "VGPIO_PCIE50", : "VGPIO_PCIE51", : "VGPIO_PCIE52", : "VGPIO_PCIE53", : "VGPIO_PCIE54", : "VGPIO_PCIE55", : "VGPIO_PCIE56", : "VGPIO_PCIE57", : "VGPIO_PCIE58", : "VGPIO_PCIE59", : "VGPIO_PCIE60", : "VGPIO_PCIE61", : "VGPIO_PCIE62", : "VGPIO_PCIE63", : "VGPIO_PCIE64", : "VGPIO_PCIE65", : "VGPIO_PCIE66", : "VGPIO_PCIE67", : "VGPIO_PCIE68", : "VGPIO_PCIE69", : "VGPIO_PCIE70", : "VGPIO_PCIE71", : "VGPIO_PCIE72", : "VGPIO_PCIE73", : "VGPIO_PCIE74", : "VGPIO_PCIE75", : "VGPIO_PCIE76", : "VGPIO_PCIE77", : "VGPIO_PCIE78", : "VGPIO_PCIE79", > Ack Corrected. https://review.coreboot.org/c/coreboot/+/73934/comment/7c4869e5_55fe63a9 PS4, Line 475: "VGPIO_USB0", : "VGPIO_USB1", : "VGPIO_USB2", : "VGPIO_USB3", : "VGPIO_USB4", : "VGPIO_USB5", : "VGPIO_USB6", : "VGPIO_USB7", : "VGPIO_USB8", : "VGPIO_USB9", : "VGPIO_USB10", : "VGPIO_USB11", > Ack Corrected. -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 9 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 12:23:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Karol Zmyslowski Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Arthur Heymans (Code Review) April 4, 2023

April 4, 2023

Attention is currently required from: Bill XIE. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/e999ba37_806b0ce4 PS3, Line 160: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); > In gma_func0_init() like this? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 5 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 12:16:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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