coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Lean Sheng Tan (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Kapil Porwal, Ivy Jian, Angel Pons, Eric Lai, Ronak Kanabar. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 11:43:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Arthur Heymans. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/57759450_150e9d87 PS3, Line 160: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); > Now it's gone? Where should it be put? -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 Apr 2023 11:16:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn: Implement HECI commands to get version details of ISHC
by Dinesh Gehlot (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Hello build bot (Jenkins), Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74005 to look at the new patch set (#13). Change subject: soc/intel/cmn: Implement HECI commands to get version details of ISHC ...................................................................... soc/intel/cmn: Implement HECI commands to get version details of ISHC The patch stores the ISHC and CSE version in the CBMEM table. It verifies CSE has been updated by comparing old and current CSE versions. If it has, the patch updates the current CSE version in the CBMEM table and communicates with the ME using the HECI command to acquire the current ISHC version. It then updates the CBMEM table with the current ISHC version. BUG=b:273661726 Test=HECI version is obtained from CSE and successfully stored Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 116 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 13 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: payloads/edk2: Set max variable size to 0x8000 for SMMSTORE
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Matt DeVillier, Stefan Reinauer. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74176 ) Change subject: payloads/edk2: Set max variable size to 0x8000 for SMMSTORE ...................................................................... Patch Set 3: (1 comment) File payloads/external/edk2/Makefile: https://review.coreboot.org/c/coreboot/+/74176/comment/c69c205a_c760c872 PS3, Line 65: 8000 just wondering. Does this takes decimal notation values and turn them into hex? -- To view, visit https://review.coreboot.org/c/coreboot/+/74176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10d2a5a0c1d729d83e0b62bb9430863317b883cc Gerrit-Change-Number: 74176 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 11:00:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn: Implement HECI commands to get version details of ISHC
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmn: Implement HECI commands to get version details of ISHC ...................................................................... Patch Set 12: (6 comments) File src/soc/intel/common/block/cse/cse_lite.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/a77f60a1_00881d1d PS12, Line 205: static bool get_partition_info(enum fpt_partition_id id, struct fw_version_resp* resp) "foo* bar" should be "foo *bar" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/e144b62c_39fe262f PS12, Line 237: if(get_partition_info(FPT_PARTITION_NAME_ISHC,&resp)) { space required after that ',' (ctx:VxO) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/02520613_a7b6b8ac PS12, Line 237: if(get_partition_info(FPT_PARTITION_NAME_ISHC,&resp)) { space required before that '&' (ctx:OxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/e4c83671_482c3037 PS12, Line 237: if(get_partition_info(FPT_PARTITION_NAME_ISHC,&resp)) { space required before the open parenthesis '(' File src/soc/intel/common/block/include/intelblocks/cse.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/d2c24d1c_bc7d3599 PS12, Line 145: struct cse_fw_ish_version_info{ missing space after struct definition Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173168): https://review.coreboot.org/c/coreboot/+/74005/comment/78a6a06f_64ddd487 PS12, Line 152: struct cse_fw_partition_info{ missing space after struct definition -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 10:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn: Implement HECI commands to get version details of ISHC
by Dinesh Gehlot (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Hello build bot (Jenkins), Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74005 to look at the new patch set (#12). Change subject: soc/intel/cmn: Implement HECI commands to get version details of ISHC ...................................................................... soc/intel/cmn: Implement HECI commands to get version details of ISHC The patch stores the ISHC and CSE version in the CBMEM table. It verifies CSE has been updated by comparing old and current CSE versions. If it has, the patch updates the current CSE version in the CBMEM table and communicates with the ME using the HECI command to acquire the current ISHC version. It then updates the CBMEM table with the current ISHC version. BUG=b:273661726 Test=HECI version is obtained from CSE and successfully stored Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 116 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 12 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bill XIE. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 3: (2 comments) File src/northbridge/intel/gm45/gm45.h: https://review.coreboot.org/c/coreboot/+/74180/comment/828df3f4_3ea35b2a PS3, Line 452: get_edid_str nit: as this has a bigger scope now, maybe call it gm45_get_lvds_edid_str ? File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/27cd9c95_5867e33a PS3, Line 160: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); Now it's gone? -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 10:55:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 5 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 04 Apr 2023 10:53:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74182 ) Change subject: mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Gerrit-Change-Number: 74182 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 04 Apr 2023 10:52:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Update pcie snoop/no-snoop latency
by Paul Menzel (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Jérémy Compostella, Ravishankar Sarawadi, Kapil Porwal. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68308 ) Change subject: soc/intel/meteorlake: Update pcie snoop/no-snoop latency ...................................................................... Patch Set 6: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68308/comment/4d62cec7_fbb19be0 PS6, Line 7: Update Increase https://review.coreboot.org/c/coreboot/+/68308/comment/025e2439_ea59efbb PS6, Line 10: This fixes an issue where pcie : was not power gating and blocked S0ix entry. I prefer to start commit message with a problem description. https://review.coreboot.org/c/coreboot/+/68308/comment/9ca39e5b_1f2187b3 PS6, Line 12: Is this a work around? Is this a hardware problem? Are these values documented in some datasheet? https://review.coreboot.org/c/coreboot/+/68308/comment/0c7666ce_6194d7dd PS6, Line 13: BUG=none Why? File src/soc/intel/meteorlake/pcie.c: https://review.coreboot.org/c/coreboot/+/68308/comment/93712beb_985c87c1 PS6, Line 9: Why do you put it here, and not `src/include/device/pciexp.h`? -- To view, visit https://review.coreboot.org/c/coreboot/+/68308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612 Gerrit-Change-Number: 68308 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 10:39:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023