coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74181 to look at the new patch set (#3). Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... mb/lenovo/x200: Read EDID in mainboard_vbt_filename() mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, making "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via get_edid_str() and use this string to call get_blc_pwm_freq_value(). This will resolve https://ticket.coreboot.org/issues/475 . Tested on my x200s with LTD121EQ3B, and x200 with LTD121EWVB. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74181/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
by Johnny Lin (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Christian Walter, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74183 ) Change subject: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Gerrit-Change-Number: 74183 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:12:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Arthur Heymans. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 2: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/4b98f06f_775f6123 PS1, Line 161: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); : pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); > > But get_edid_str() may be called elsewhere. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74182 to look at the new patch set (#3). Change subject: mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz ...................................................................... mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz The vendor sets BLC_PWM_CTL to 0x31313131. This value seems working well on the x200 with this panel, which is said to be LED. Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74182/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Gerrit-Change-Number: 74182 Gerrit-PatchSet: 3 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bill XIE. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74180 to look at the new patch set (#2). Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... nb/intel/gm45: Export EDID-reading routine as a function It will cache decoded EDID string in a static array. If called more than once, a pointer to the static array is directly returned, without reading EDID again. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 46 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74180/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74181 to look at the new patch set (#2). Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... mb/lenovo/x200: Read EDID in mainboard_vbt_filename() mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, making "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via get_edid_str() and use this string to call get_blc_pwm_freq_value(). This will resolve https://ticket.coreboot.org/issues/475 . Tested on my x200s with LTD121EQ3B, and x200 with LTD121EQ3B. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74181/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Default to X2APIC support
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74184 ) Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Gerrit-Change-Number: 74184 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:05:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Default to X2APIC support
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74184 ) Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/xeon_sp/spr/Kconfig: https://review.coreboot.org/c/coreboot/+/74184/comment/e3f0cc4a_fbe1d7ef PS1, Line 11: select DEFAULT_X2APIC_RUNTIME We could enable this if MAX_CPUS >= 256 -- To view, visit https://review.coreboot.org/c/coreboot/+/74184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Gerrit-Change-Number: 74184 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74183 ) Change subject: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Gerrit-Change-Number: 74183 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:04:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 9: Code-Review+1 (4 comments) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/470c7448_9b7d8ee0 PS9, Line 31: MAX_SOCKET_UPD Help text says: > This is used for configuring common SPR UPD tables which their sizes > depend on the socket number. Since it's the maximal socket number for > the common UPD tables, mainboard should not overwrite it. Why does it have to be overridden here? Why not use MAX_SOCKET instead? File src/mainboard/ibm/sbp1/bootblock.c: https://review.coreboot.org/c/coreboot/+/73392/comment/cf532532_b7c8d18e PS9, Line 23: For ArcherCity CRB, only SUART1 is used. Drop this? File src/mainboard/ibm/sbp1/dsdt.asl: https://review.coreboot.org/c/coreboot/+/73392/comment/e2939500_7539dc8d PS9, Line 10: // OEM revision Is it? File src/mainboard/ibm/sbp1/romstage.c: https://review.coreboot.org/c/coreboot/+/73392/comment/d916aca4_2a1e594b PS9, Line 345: sktbmp[0] = BIT(1) | BIT(2); : sktbmp[1] = BIT(1) | BIT(5); : sktbmp[2] = BIT(1) | BIT(4); : sktbmp[3] = BIT(1) | BIT(4); It might be useful to have macros for these -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 09:04:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023