coreboot-gerrit April 2023

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bill XIE. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/eaefabb3_53bcb8c4 PS1, Line 161: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); : pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); This is not needed to get EDID. Move into func0_init. -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:05:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74183 ) Change subject: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Gerrit-Change-Number: 74183 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 07:51:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 8: Code-Review+1 (4 comments) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/1a3be99e_1443e8c0 PS8, Line 14: select DEFAULT_X2APIC Should be set at SOC level? https://review.coreboot.org/c/coreboot/+/73392/comment/29834454_656c278e PS8, Line 40: config DEBUG_SMI : default y Why? File src/mainboard/ibm/sbp1/romstage.c: https://review.coreboot.org/c/coreboot/+/73392/comment/4f661193_cd5f7f58 PS8, Line 320: mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; Same at soc level. https://review.coreboot.org/c/coreboot/+/73392/comment/cc01221e_a7fff26d PS8, Line 325: /* Set Attempt Fast Boot to enable. */ : /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on warm boots.*/ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ : mupd->FspmConfig.AttemptFastBoot = 0x1; : : /* Set Attempt Fast Cold Boot to enable. */ : /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on cold boots. */ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ : mupd->FspmConfig.AttemptFastBootCold = 0x1; Same settings are set at soc level. -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 07:51:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 8: (1 comment) File src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173150): https://review.coreboot.org/c/coreboot/+/73392/comment/d0732f13_c979260d PS8, Line 243: PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_RX_STATE | \ Avoid unnecessary line continuations -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 07:43:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74183 ) Change subject: soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems ...................................................................... soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/soc_acpi.c 1 file changed, 41 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/74183/1 diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index d9d82ac..619e5bb 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -86,7 +86,8 @@ fadt->x_gpe1_blk.addrh = 0x0; } -static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_iou_pci_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, + bool stack_enabled) { /* Stacks 0 (TYPE_UBOX_IIO) @@ -105,16 +106,6 @@ acpigen_write_resourcetemplate_header(); - /* - * ACPI spec requires that each bus device (stack) has a valid - * resource template. Disabled devices still need a valid _CRS - * although the values are ignored. The FWTS sanity check does - * not pass when using the HOB stack resources to generate the - * _CRS resource template for disabled stacks, so we provide a - * zeroed resource template to satisfy both the spec and FWTS. - */ - const bool stack_enabled = ri->Personality < TYPE_RESERVED; - /* Bus Resource */ if (stack_enabled) { /* For stack with CXL device, the PCIe bus resource is BusBase only. */ @@ -178,7 +169,7 @@ acpigen_write_resourcetemplate_footer(); } -static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks 1 .. 5 (TYPE_UBOX_IIO) @@ -194,7 +185,7 @@ acpigen_write_resourcetemplate_header(); - if (ri->Personality < TYPE_RESERVED) { + if (stack_enabled) { /* bus resource, from (BusBase + 1) to BusLimit */ acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase + 1, ri->BusLimit, 0x0, (ri->BusLimit - ri->BusBase)); @@ -229,7 +220,7 @@ acpigen_write_resourcetemplate_footer(); } -static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks 8 .. B (TYPE_DINO) @@ -298,7 +289,7 @@ acpigen_write_name(tres); acpigen_write_resourcetemplate_header(); - if (ri->Personality < TYPE_RESERVED) { + if (stack_enabled) { acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0, (bus_limit - bus_base + 1)); @@ -327,7 +318,7 @@ } } -static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_ubox_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { /* Stacks D .. E (TYPE_UBOX) @@ -348,7 +339,7 @@ acpigen_write_name(tres); acpigen_write_resourcetemplate_header(); - if (ri->Personality >= TYPE_RESERVED) + if (!stack_enabled) acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0); else if (i == 0) acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1); @@ -365,12 +356,12 @@ * Add a DSDT ACPI Name field for STACK enable setting. * This is retrieved by the device _STA defined in iiostack.asl */ -static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri) +static void create_dsdt_stack_sta(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled) { char stack_sta[16]; snprintf(stack_sta, sizeof(stack_sta), "ST%d%X", socket, stack); - if (ri->Personality >= TYPE_RESERVED) + if (!stack_enabled) acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_OFF); else acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); @@ -378,6 +369,8 @@ void uncore_inject_dsdt(const struct device *device) { + bool stack_enabled; + /* Only add RTxx entries once. */ if (device->bus->secondary != 0) return; @@ -402,27 +395,28 @@ /* The _CSR generation must match SPR iiostack.asl. */ const IIO_UDS *hob = get_iio_uds(); - /* TODO: DSDT uses CONFIG_MAX_SOCKET while PlatformData.numofIIO is the actual number - of CPUs plugged in, although it doesn't cause serious errors when not all CPUs are - plugged in, they should be in sync. */ - for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ + for (uint8_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; + stack_enabled = hob->PlatformData.IIO_resource[socket].Valid && + ri->Personality < TYPE_RESERVED; + printk(BIOS_DEBUG, "%s processing socket: %d, stack: %d, type: %d\n", __func__, socket, stack, ri->Personality); if (stack <= IioStack5) { // TYPE_UBOX_IIO - create_dsdt_iou_pci_resource(socket, stack, ri); - create_dsdt_iou_cxl_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled); + create_dsdt_iou_cxl_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO - create_dsdt_dino_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_dino_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } else if (stack == IioStack13) { // TYPE_UBOX - create_dsdt_ubox_resource(socket, stack, ri); - create_dsdt_stack_sta(socket, stack, ri); + create_dsdt_ubox_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/74183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Gerrit-Change-Number: 74183 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. Hello build bot (Jenkins), David Hendricks, Shuo Liu, Nill Ge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73392 to look at the new patch set (#8). Change subject: mb/ibm: Add IBM SBP1 ...................................................................... mb/ibm: Add IBM SBP1 The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs Test: The board boots to Linux with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 --- A src/mainboard/ibm/Kconfig A src/mainboard/ibm/Kconfig.name A src/mainboard/ibm/sbp1/Kconfig A src/mainboard/ibm/sbp1/Kconfig.name A src/mainboard/ibm/sbp1/Makefile.inc A src/mainboard/ibm/sbp1/acpi/platform.asl A src/mainboard/ibm/sbp1/board.fmd A src/mainboard/ibm/sbp1/board_info.txt A src/mainboard/ibm/sbp1/bootblock.c A src/mainboard/ibm/sbp1/devicetree.cb A src/mainboard/ibm/sbp1/dsdt.asl A src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h A src/mainboard/ibm/sbp1/ramstage.c A src/mainboard/ibm/sbp1/romstage.c 14 files changed, 890 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73392/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix GPIO settings
by Jan Samek (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74201 ) Change subject: mb/siemens/mc_ehl2: Fix GPIO settings ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Gerrit-Change-Number: 74201 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 07:34:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Fix GPIO settings
by Mario Scheithauer (Code Review) 04 Apr '23

04 Apr '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74201 ) Change subject: mb/siemens/mc_ehl2: Fix GPIO settings ...................................................................... mb/siemens/mc_ehl2: Fix GPIO settings With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no longer used. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/74201/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c index 72994bb..20a89c6 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c @@ -72,8 +72,7 @@ /* Community 2 - GpioGroup DSW */ PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), /* ACPRESENT */ PAD_NC(GPD9, NONE), /* Not connected */ - /* ONBOARD_X4_PCIE_SLOT1_RESET_N */ - PAD_CFG_GPO(GPD11, 1, PLTRST), + PAD_NC(GPD11, NONE), /* Not connected */ /* Community 3 - GpioGroup GPP_S */ PAD_NC(GPP_S0, NONE), /* Not connected */ @@ -110,6 +109,7 @@ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */ + PAD_NC(GPP_C8, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Gerrit-Change-Number: 74201 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Uday Bhat, Jairaj Arava. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: (1 comment) Patchset: PS13: > You mean in comment or commit message - as it is bit long to accomodate here Can you please add below line in the commit section ? ``` TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 06:54:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Uday Bhat (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Jairaj Arava. Uday Bhat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: (1 comment) Patchset: PS13: > > b:275538390 updated with the verification steps […] You mean in comment or commit message - as it is bit long to accomodate here -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 06:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023