coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Alexander Couzens. Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... mb/lenovo/x200: Read EDID in mainboard_vbt_filename() mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, making "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via get_edid_str() and use this string to call get_blc_pwm_freq_value(). This will resolve https://ticket.coreboot.org/issues/475 . Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 --- M src/mainboard/lenovo/x200/blc.c 1 file changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74181/1 diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index ef2dbb1..02b16d1 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -4,6 +4,7 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> +#include <device/pci.h> #include <drivers/intel/gma/opregion.h> static const struct blc_pwm_t blc_entries[] = { @@ -36,9 +37,8 @@ const char *mainboard_vbt_filename(void) { - u16 pwm_freq; - - pwm_freq = get_blc_pwm_freq_value(NULL); + struct device *gma = pcidev_path_on_root(PCI_DEVFN(0x2, 0)); + u16 pwm_freq = gma ? get_blc_pwm_freq_value(get_edid_str(gma)) : 0; if (pwm_freq == 0) { printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... nb/intel/gm45: Export EDID-reading routine as a function It will cache decoded EDID string in a static array. If called more than once, a pointer to the static array is directly returned, without reading EDID again. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca --- M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/gma.c 2 files changed, 49 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74180/1 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index f28c6d1..089d19a 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -447,6 +447,9 @@ u16 get_blc_pwm_freq_value(const char *edid_ascii_string); #include <device/device.h> +#include <edid.h> + +const char *get_edid_str(struct device *dev); struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8043822..a59bcea 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -143,18 +143,19 @@ reg8)); } -static void gma_func0_init(struct device *dev) +const char *get_edid_str(struct device *dev) { u8 *mmio; u8 edid_data_lvds[128]; struct edid edid_lvds; - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; + static char edid_str[EDID_ASCII_STRING_LENGTH + 1]; - intel_gma_init_igd_opregion(); + if (edid_str[0]) + return edid_str; gtt_res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!gtt_res) - return; + return NULL; mmio = res2mmio(gtt_res, 0, 0); /* @@ -163,9 +164,33 @@ */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); memset(mmio + 2 * MiB, 0, 2 * MiB); + pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); - if (CONFIG(NO_GFX_INIT)) - pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); + printk(BIOS_DEBUG, "LVDS EDID\n"); + intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, + edid_data_lvds, sizeof(edid_data_lvds)); + intel_gmbus_stop(mmio + GMBUS0); + + if (decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds) + != EDID_CONFORMANT) + return NULL; + memcpy(edid_str, edid_lvds.ascii_string, sizeof(edid_str)); + return edid_str; +} + +static void gma_func0_init(struct device *dev) +{ + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; + const char *edid_str; + + intel_gma_init_igd_opregion(); + + edid_str = get_edid_str(dev); + if (!edid_str) + printk(BIOS_ERR, "Failed to obtain LVDS EDID string!\n"); + + if (!CONFIG(NO_GFX_INIT)) + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { /* PCI Init, will run VBIOS */ @@ -173,14 +198,8 @@ pci_dev_init(dev); } - printk(BIOS_DEBUG, "LVDS EDID\n"); - intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, - edid_data_lvds, sizeof(edid_data_lvds)); - intel_gmbus_stop(mmio + GMBUS0); - decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); - /* Post VBIOS init */ - gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); + gma_pm_init_post_vbios(dev, edid_str); if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value()
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74179 ) Change subject: nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value() ...................................................................... nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value() IF its first call is get_blc_pwm_freq_value(NULL), null dereference will occur. Now when the parameter is NULL, it will return the value of the static blc_pwm_freq directly, so the original behavior is kept. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5 --- M src/northbridge/intel/gm45/gma.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/74179/1 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 7df9106..8043822 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -67,7 +67,8 @@ int i; int blc_array_len; - if (blc_pwm_freq > 0) + /* Prevent null-deref on strcmp() below */ + if (blc_pwm_freq > 0 || !edid_ascii_string) return blc_pwm_freq; blc_array_len = get_blc_values(&blc_pwm); -- To view, visit https://review.coreboot.org/c/coreboot/+/74179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5 Gerrit-Change-Number: 74179 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Anil Kumar K (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Anil Kumar K, Uday Bhat, Jairaj Arava. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72881/comment/b70dc693_b93b56a6 PS13, Line 9: Enable BT I2S offload feature. : SSP1 needs to be used for BT offload and program vGPIO. > Please add a blank line between paragraphs or do not wrap lines after a sentence ends. Ack https://review.coreboot.org/c/coreboot/+/72881/comment/3801a720_dfd9d5ce PS13, Line 10: SSP1 needs to be used for BT offload and program vGPIO. > According to the schematics? Yes . I2S0 and I2S2 lines are being used for speaker adn HP connections on daughter board. So we have enabled BT offload on SSP1 https://review.coreboot.org/c/coreboot/+/72881/comment/59f60835_d5bd40ec PS13, Line 13: Playback > Play back Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 02:17:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Anil Kumar K (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Uday Bhat, Jairaj Arava. Anil Kumar K has uploaded a new patch set (#14) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... mb/google/rex: Enable audio BT offload This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Play back through BT Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/rex0/fw_config.c 2 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/72881/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Add FW_CONFIG
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Eric Lai, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74102 to look at the new patch set (#13). Change subject: mb/google/myst: Add FW_CONFIG ...................................................................... mb/google/myst: Add FW_CONFIG Add initial FW_CONFIG for the myst program. BUG=b: TEST=builds Cq-Depend: chrome-internal:5674351 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19 --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/variants/myst/overridetree.cb 2 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/74102/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19 Gerrit-Change-Number: 74102 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74110 to look at the new patch set (#13). Change subject: mb/google/myst: Add eSPI configuration ...................................................................... mb/google/myst: Add eSPI configuration Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/bootblock.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 5 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74110/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74110 ) Change subject: mb/google/myst: Add eSPI configuration ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/myst/variants/baseboard/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173113): https://review.coreboot.org/c/coreboot/+/74110/comment/6b02d3a6_d4aa9dd4 PS12, Line 220: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 00:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add DXIO descriptors
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74178 ) Change subject: mb/google/myst: Add DXIO descriptors ...................................................................... mb/google/myst: Add DXIO descriptors Add Myst DXIO descriptors using info from AMD and skyrim board shematics. BUG=b:276744321 TEST=builds Change-Id: I12726499ee644b158cc06ed102bb1c8559e1a73c --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 2 files changed, 97 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/74178/1 diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 9d3b15b..64255f2 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -1,11 +1,86 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <soc/gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +static const fsp_dxio_descriptor skyrim_sbna_dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ2, + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .gpio_group_id = GPIO_6, + .clk_req = CLK_REQ0, + }, +}; + +static const fsp_ddi_descriptor skyrim_sbna_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - Unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + }, +}; + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - /* TODO(b/276744321): Initialize DXIO and DDI descriptors */ + *dxio_descs = skyrim_sbna_dxio_descriptors; + *dxio_num = ARRAY_SIZE(skyrim_sbna_dxio_descriptors); + *ddi_descs = skyrim_sbna_ddi_descriptors; + *ddi_num = ARRAY_SIZE(skyrim_sbna_ddi_descriptors); } diff --git a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h index 5f127ba..9c52732 100644 --- a/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,12 @@ #define __BASEBOARD_VARIANTS_H__ #include <amdblocks/gpio.h> +#include <platform_descriptors.h> +#include <soc/pci_devs.h> + +#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN +#define SD_DEVFN PCIE_GPP_2_1_DEVFN +#define NVME_DEVFN PCIE_GPP_2_2_DEVFN /* This function provides base GPIO configuration table. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12726499ee644b158cc06ed102bb1c8559e1a73c Gerrit-Change-Number: 74178 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/myst: Add eSPI configuration
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74110 to look at the new patch set (#12). Change subject: mb/google/myst: Add eSPI configuration ...................................................................... mb/google/myst: Add eSPI configuration Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/bootblock.c M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h 5 files changed, 91 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/74110/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/74110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Gerrit-Change-Number: 74110 Gerrit-PatchSet: 12 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

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