coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: mb/google/myst: Add smihandler
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Eric Lai, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Hello build bot (Jenkins), Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74100 to look at the new patch set (#11). Change subject: mb/google/myst: Add smihandler ...................................................................... mb/google/myst: Add smihandler Add SMI handler code for Myst platform. BUG=b:275858191 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 --- M src/mainboard/google/myst/variants/baseboard/Makefile.inc A src/mainboard/google/myst/variants/baseboard/smihandler.c 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74100/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/74100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Gerrit-Change-Number: 74100 Gerrit-PatchSet: 11 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/phoenix:Commit with lint warning fix
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Anand Vaikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/73507 ) Change subject: soc/amd/phoenix:Commit with lint warning fix ...................................................................... Abandoned Lint warning has been removed, the fix is not necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/73507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1f67d31d027425d1d28cf42347a4eae21462c9 Gerrit-Change-Number: 73507 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: soc/amd/phoenix:Commit with lint warning fix
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Paul Menzel, Fred Reitberger. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73507 ) Change subject: soc/amd/phoenix:Commit with lint warning fix ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/73507/comment/69f416fc_8474d074 PS3, Line 7: soc/amd/phoenix:Commit with lint warning fix > Please improve the commit message. Thanks for your review, as this lint warning has been removed I am abandoning this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/73507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1f67d31d027425d1d28cf42347a4eae21462c9 Gerrit-Change-Number: 73507 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 00:08:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe...
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Anand Vaikar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74199 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe SSD0 device sits behind the PCIe bridge 0.2.4(BDF) on mayan. Updated the correct bridge device. TEST: Builds, M.2 SSD0 device gets enumerated. BUG: N/A. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I575f61cfc84bc07c389da7826c5f150e57aaec07 Gerrit-Change-Number: 74199 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe...
by build bot (Jenkins) (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74199 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe SSD0 device sits behind the PCIe bridge 0.2.4(BDF) on mayan. Updated the correct bridge device. TEST: Builds, M.2 SSD0 device gets enumerated. BUG: N/A. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173101): https://review.coreboot.org/c/coreboot/+/74199/comment/51f41b98_f19cd883 PS1, Line 6: Possible long commit subject (prefer a maximum 65 characters) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-173101): https://review.coreboot.org/c/coreboot/+/74199/comment/d81c48d8_59aa34e9 PS1, Line 6: Subject line should not end with a period. -- To view, visit https://review.coreboot.org/c/coreboot/+/74199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I575f61cfc84bc07c389da7826c5f150e57aaec07 Gerrit-Change-Number: 74199 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Apr 2023 00:03:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe...
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74199 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe SSD0 device sits behind the PCIe bridge 0.2.4(BDF) on mayan. Updated the correct bridge device. TEST: Builds, M.2 SSD0 device gets enumerated. BUG: N/A. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 PCIe NVMe SSD0 device sits behind the PCIe bridge 0.2.4(BDF) on mayan. Updated the correct bridge device. TEST: Builds, M.2 SSD0 device gets enumerated. BUG: N/A. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Change-Id: I575f61cfc84bc07c389da7826c5f150e57aaec07 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/74199/1 diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 9d1a4b3..697db12 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -160,7 +160,7 @@ device ref iommu on end device ref gpp_bridge_2_1 on end # GBE device ref gpp_bridge_2_2 on end # WIFI - device ref gpp_bridge_2_3 on end # NVMe SSD + device ref gpp_bridge_2_4 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) -- To view, visit https://review.coreboot.org/c/coreboot/+/74199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I575f61cfc84bc07c389da7826c5f150e57aaec07 Gerrit-Change-Number: 74199 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74112/comment/769c1e30_a4d4d066 PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe > Are the comments correct? The ordering of PCIe nets on the schematic look different. […] I misspoke, it's not the lanes, but they are grouping descriptors. I'll double check the schematic -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 23:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Mark Hasemeyer (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Karthik Ramasubramanian. Mark Hasemeyer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 13: (1 comment) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74112/comment/9c606f39_e0638e9f PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe > These are aliases set by the SoC(https://source.chromium. […] Are the comments correct? The ordering of PCIe nets on the schematic look different. Also NVMe uses 4 lanes. Not sure if that matters here. -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 23:41:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable PCIe devices in devicetree
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74112 ) Change subject: mb/google/myst: Enable PCIe devices in devicetree ...................................................................... Patch Set 13: (2 comments) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/74112/comment/0bed68f2_1780ce19 PS8, Line 43: device domain 0 on > Do we need `device ref iommu on end` so we can access these devices through the IOMMU? Yea, good catch. Covered in https://review.coreboot.org/c/coreboot/+/74177 https://review.coreboot.org/c/coreboot/+/74112/comment/0be9015f_416b7dcb PS8, Line 52: device ref gpp_bridge_2_4 on end # NVMe > I'm not an expert here. Why are these `bridge_2_1`, `bridge_2_2`, etc. […] These are aliases set by the SoC(https://source.chromium.org/chromium/chromiumos/third_party/coreboot/+/…, and are referenced such that the first number is the PCI device and the second is the lane -- To view, visit https://review.coreboot.org/c/coreboot/+/74112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Gerrit-Change-Number: 74112 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 23:33:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/myst: Enable iommu
by Jon Murphy (Code Review) 04 Apr '23

04 Apr '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74177 ) Change subject: mb/google/myst: Enable iommu ...................................................................... mb/google/myst: Enable iommu Enable iommu in devicetree for myst in order to allow kernel to load and initialize IOMMU. Bug=b:276805280 TEST=builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811 --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/74177/1 diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 7980101..10d022d 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -6,6 +6,7 @@ device pnp 0c09.0 alias chrome_ec on end end end + device ref iommu on end end # domain device ref uart_0 on end # UART0 end # chip soc/amd/phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/74177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811 Gerrit-Change-Number: 74177 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023