coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: mb/intel: add Archer City CRB support
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Simon Chou, Johnny Lin, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add Archer City CRB support ...................................................................... Patch Set 28: (1 comment) Patchset: PS28: The multisocket support depends on Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 28 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Juan Sanchez Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Juan Sanchez Gerrit-Comment-Date: Tue, 04 Apr 2023 06:49:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/mtlrvp: Update MTLRVP Flash Layout
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73378 ) Change subject: mb/google/mtlrvp: Update MTLRVP Flash Layout ...................................................................... mb/google/mtlrvp: Update MTLRVP Flash Layout This patch updates the MTLRVP flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: SI_EC: Removed RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:271407315 TEST=Able to enable CSE update on MTLRVP and have free space to add one more PUNIT FW to support different SoC stepping. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd M src/mainboard/intel/mtlrvp/chromeos.fmd 2 files changed, 66 insertions(+), 33 deletions(-) Approvals: build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, approved Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd index 579a7bd..bd250f5f 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd @@ -4,39 +4,33 @@ SI_ME } SI_BIOS 23M { - RW_SECTION_A 7M { - VBLOCK_A 64K + RW_SECTION_A 7604K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_MISC 1M { + RW_MISC 152K { + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K - } - # The RW_SPD_CACHE region is only used for variants that use DDRx memory. - # It is placed in the common `chromeos.fmd` file because it is only 4K and there - # is free space in the RW_MISC region that cannot be easily reclaimed because - # the RW_SECTION_B must start on the 16M boundary. - RW_SPD_CACHE(PRESERVE) 4K - RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, # because the SPI flash is memory-mapped into two non- # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 64K + RW_SECTION_B 7604K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index 9fc7d7b..22dbff5 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -1,36 +1,34 @@ FLASH 32M { SI_ALL 9M { SI_DESC 16K - SI_EC 512K SI_ME } SI_BIOS 23M { - RW_SECTION_A 6M { - VBLOCK_A 64K + RW_SECTION_A 7092K { + VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K + ME_RW_A(CBFS) 4400K } - RW_LEGACY(CBFS) 2M - RW_MISC 1M { + RW_MISC 152K { UNIFIED_MRC_CACHE 128K { RECOVERY_MRC_CACHE 64K RW_MRC_CACHE 64K } - RW_ELOG(PRESERVE) 16K - RW_SHARED 16K { - SHARED_DATA 8K - VBLOCK_DEV 8K + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K } RW_VPD(PRESERVE) 8K - RW_NVRAM(PRESERVE) 24K + RW_NVRAM(PRESERVE) 8K } - RW_SECTION_B 6M { - VBLOCK_B 64K + RW_SECTION_B 7092K { + VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K + ME_RW_B(CBFS) 4400K } + RW_LEGACY(CBFS) 1M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 8M { -- To view, visit https://review.coreboot.org/c/coreboot/+/73378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Gerrit-Change-Number: 73378 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add fmd for debug FSP
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74193 ) Change subject: mb/intel/mtlrvp: Add fmd for debug FSP ...................................................................... mb/intel/mtlrvp: Add fmd for debug FSP Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for MTL-P RVP flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. BUG=b:271407315 TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Signed-off-by: Usha P <usha.p(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd 2 files changed, 79 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, approved Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 0af0529..8a66ea0 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -70,6 +70,7 @@ default "mtlrvp" config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" config MAINBOARD_FAMILY diff --git a/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd new file mode 100644 index 0000000..579a7bd --- /dev/null +++ b/src/mainboard/intel/mtlrvp/chromeos.debug-fsp.fmd @@ -0,0 +1,54 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_ME + } + SI_BIOS 23M { + RW_SECTION_A 7M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 3008K + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + # The RW_SPD_CACHE region is only used for variants that use DDRx memory. + # It is placed in the common `chromeos.fmd` file because it is only 4K and there + # is free space in the RW_MISC region that cannot be easily reclaimed because + # the RW_SECTION_B must start on the 16M boundary. + RW_SPD_CACHE(PRESERVE) 4K + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 3008K + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 8M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Gerrit-Change-Number: 74193 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Uday Bhat, Jairaj Arava. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: Code-Review+2 (1 comment) Patchset: PS13: > b:275538390 updated with the verification steps Do you mind adding the `TEST` statement here as well ? -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 06:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Uday Bhat (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Jairaj Arava. Uday Bhat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: (1 comment) Patchset: PS13: > I’d say that information could got into the commit message. b:275538390 updated with the verification steps -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 04:38:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74075 to look at the new patch set (#4). Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence updated the correct bridge number in the device tree. TEST: Builds, the device enumerates. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74075/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 4 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74075 to look at the new patch set (#3). Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF),hence updated the correct bridge number in the device tree. TEST: Builds, the device enumerates. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74075/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74075 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74075/comment/73495ff4_c37fbb83 PS1, Line 7: Update the correct PCIe bridge for M.2 NVME SSD0 > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/74075/comment/fddd3f33_8894b0be PS1, Line 7: mb/amd/mayan:Update the correct PCIe bridge for M.2 NVME SSD0 > Please add a space after the colon. Done https://review.coreboot.org/c/coreboot/+/74075/comment/c60faa46_9063ca57 PS1, Line 8: > Please elaborate. Why is the new one correct? […] Done Patchset: PS2: Thanks for the review, I have addressed the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Apr 2023 04:30:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Anand Vaikar, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74075 to look at the new patch set (#2). Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 NVME SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF),hence updated the correct bridge number in the device tree. TEST: Builds, the device enumerates. Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74075/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Add DTT thermal settings for policies
by Sumeet R Pawnikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, John Zhao, Ivy Jian, Eric Lai, Peter Ou. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71166 ) Change subject: mb/google/rex: Add DTT thermal settings for policies ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Peter need to collect the information from Brya. […] @Eric, any update on this? Can we get this review? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/71166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Gerrit-Change-Number: 71166 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 03:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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