coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: Revert "mb/starlabs/*: Remove sleepstates.asl"
by Lean Sheng Tan (Code Review) 04 Apr '23

04 Apr '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73894 ) Change subject: Revert "mb/starlabs/*: Remove sleepstates.asl" ...................................................................... Revert "mb/starlabs/*: Remove sleepstates.asl" This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/starlabs/lite/dsdt.asl M src/mainboard/starlabs/starbook/dsdt.asl 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Benjamin Doron: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/lite/dsdt.asl b/src/mainboard/starlabs/lite/dsdt.asl index 7b2918b..13a1eb6 100644 --- a/src/mainboard/starlabs/lite/dsdt.asl +++ b/src/mainboard/starlabs/lite/dsdt.asl @@ -26,6 +26,8 @@ #include <drivers/pc80/pc/ps2_controller.asl> } + #include <southbridge/intel/common/acpi/sleepstates.asl> + /* Star Labs EC */ #include <ec/starlabs/merlin/acpi/ec.asl> diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index cacbf3d..0688949 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -39,6 +39,8 @@ #include <drivers/pc80/pc/ps2_controller.asl> } + #include <southbridge/intel/common/acpi/sleepstates.asl> + /* Star Labs EC */ #include <ec/starlabs/merlin/acpi/ec.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/73894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Gerrit-Change-Number: 73894 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: arch/x86/car.ld: Accomodate for FSP spec violation on Xeon-SP
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Arthur Heymans, Anjaneya "Reddy" Chagam, Jonathan Zhang, Jay Talbott, Johnny Lin, Christian Walter, Patrick Rudolph, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61164 ) Change subject: arch/x86/car.ld: Accomodate for FSP spec violation on Xeon-SP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee Gerrit-Change-Number: 61164 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:58:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/acer/aspire_vn7_572g: Fix internal speakers again
by Angel Pons (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Benjamin Doron. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73869 ) Change subject: mb/acer/aspire_vn7_572g: Fix internal speakers again ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73869/comment/218d5a2d_4372b54d PS1, Line 10: restores restore https://review.coreboot.org/c/coreboot/+/73869/comment/22563c99_2b45bcb9 PS1, Line 15: Further investigation required to know why this works. Do you have a coreboot log before and after this change? -- To view, visit https://review.coreboot.org/c/coreboot/+/73869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb676c6ca4edf8c5fdd4effbc71b60acc5de863f Gerrit-Change-Number: 73869 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:58:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bill XIE. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/116cdc9d_73e916d2 PS1, Line 161: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); : pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); > But get_edid_str() may be called elsewhere. Won't PCI_COMMAND_MASTER being kept by GMA be problematic? A reason more why this function should not touch it. It should return edid string, not clear PCI bits. -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:39:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Default to X2APIC support
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74184 ) Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Gerrit-Change-Number: 74184 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:39:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Paul Menzel, David Hendricks, Shuo Liu, Arthur Heymans, Nill Ge. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add IBM SBP1 ...................................................................... Patch Set 9: (4 comments) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/f87f716f_9a0a5cbf PS8, Line 14: select DEFAULT_X2APIC > Should be set at SOC level? Moved to soc level https://review.coreboot.org/c/coreboot/+/73392/comment/bffae92a_8bf22f16 PS8, Line 40: config DEBUG_SMI : default y > Why? removed File src/mainboard/ibm/sbp1/romstage.c: https://review.coreboot.org/c/coreboot/+/73392/comment/4d4b6dda_c508e493 PS8, Line 320: mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; > Same at soc level. Done https://review.coreboot.org/c/coreboot/+/73392/comment/4f384ede_042e8676 PS8, Line 325: /* Set Attempt Fast Boot to enable. */ : /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on warm boots.*/ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ : mupd->FspmConfig.AttemptFastBoot = 0x1; : : /* Set Attempt Fast Cold Boot to enable. */ : /* Enable - Portions of memory reference code will be skipped */ : /* when possible to increase boot speed on cold boots. */ : /* Disable - Disables this feature. */ : /* Auto - Sets it to the MRC default setting. */ : mupd->FspmConfig.AttemptFastBootCold = 0x1; > Same settings are set at soc level. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Default to X2APIC support
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74184 ) Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support ...................................................................... soc/intel/xeon_sp/spr: Default to X2APIC support When more than 255 CPU cores are present on a board the X2APIC must be used. Select DEFAULT_X2APIC_RUNTIME to support X2APIC by default when a mainboard enables it in the devicetree. Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/74184/1 diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 7aa1fec..832aab5 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -8,6 +8,7 @@ select SAVE_MRC_AFTER_FSPS select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select DISABLE_ACPI_HIBERNATE + select DEFAULT_X2APIC_RUNTIME config CHIPSET_DEVICETREE string -- To view, visit https://review.coreboot.org/c/coreboot/+/74184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Gerrit-Change-Number: 74184 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: mb/ibm: Add IBM SBP1
by Patrick Rudolph (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Patrick Rudolph, Paul Menzel, David Hendricks, Shuo Liu, Nill Ge. Hello build bot (Jenkins), David Hendricks, Shuo Liu, Arthur Heymans, Nill Ge, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73392 to look at the new patch set (#9). Change subject: mb/ibm: Add IBM SBP1 ...................................................................... mb/ibm: Add IBM SBP1 The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs Test: The board boots to Linux with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 --- A src/mainboard/ibm/Kconfig A src/mainboard/ibm/Kconfig.name A src/mainboard/ibm/sbp1/Kconfig A src/mainboard/ibm/sbp1/Kconfig.name A src/mainboard/ibm/sbp1/Makefile.inc A src/mainboard/ibm/sbp1/acpi/platform.asl A src/mainboard/ibm/sbp1/board.fmd A src/mainboard/ibm/sbp1/board_info.txt A src/mainboard/ibm/sbp1/bootblock.c A src/mainboard/ibm/sbp1/devicetree.cb A src/mainboard/ibm/sbp1/dsdt.asl A src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h A src/mainboard/ibm/sbp1/ramstage.c A src/mainboard/ibm/sbp1/romstage.c 14 files changed, 855 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/73392/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Arthur Heymans. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/5113b925_942febfd PS1, Line 161: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); : pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); > This is not needed to get EDID. Move into func0_init. But get_edid_str() may be called elsewhere. Won't PCI_COMMAND_MASTER being kept by GMA be problematic? -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:24:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023