coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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5761 discussions

[M] Change in coreboot[master]: nb/intel/gm45: Export EDID-reading routine as a function
by Bill XIE (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Arthur Heymans. Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 ) Change subject: nb/intel/gm45: Export EDID-reading routine as a function ...................................................................... Patch Set 1: (1 comment) File src/northbridge/intel/gm45/gma.c: https://review.coreboot.org/c/coreboot/+/74180/comment/5113b925_942febfd PS1, Line 161: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB); : pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); > This is not needed to get EDID. Move into func0_init. But get_edid_str() may be called elsewhere. Won't PCI_COMMAND_MASTER being kept by GMA be problematic? -- To view, visit https://review.coreboot.org/c/coreboot/+/74180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca Gerrit-Change-Number: 74180 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:24:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Uday Bhat (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Uday Bhat, Jairaj Arava. Uday Bhat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 14: (1 comment) Patchset: PS13: > b:275538390 updated with the verification steps BT offload was verified on Rex with I2S audio configuration Changes and execution procedure as below Coreboot changes built with https://review.coreboot.org/c/coreboot/+/72881 Kernel driver changes Patches from link - https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 279e52d6b9f3 ASoC: SOF: ipc4-pcm: support multiple configs for BE DAIs f19f24d47900 ASoC: Intel: sof_rt5682: Update BT offload config for MTL RVP 54e288766906 ASoC: Intel: sof_rt5682: Update BT offload config for Rex Build and update kernel Topology changes Build topology 2 using latest branch from https://github.com/thesofproject/sof update the topology in DUT and reboot Execution aplay, arecord will list as bluetooth with device number aplay -D hw:<card no>,<device no> -c <no of channels> -r <sampling rate> -f <format> <location/playback-file> arecord -D hw:<card no>,<device no> -c <no of channels> -r <sampling rate> -f <format> <location/capture-file> -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Attention: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:24:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable CSE pre-cpu timestamps
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73759 ) Change subject: mb/google/rex: Enable CSE pre-cpu timestamps ...................................................................... mb/google/rex: Enable CSE pre-cpu timestamps Enables pre-cpu boot timestamps from cse. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot on rex, check "cbmem -t" Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73759 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 1a052a6..6cea7fc 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -26,6 +26,7 @@ select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 config BOARD_GOOGLE_BASEBOARD_REX def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/73759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Gerrit-Change-Number: 73759 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73713 ) Change subject: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table ...................................................................... soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/cse_telemetry.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h M src/soc/intel/meteorlake/Makefile.inc A src/soc/intel/meteorlake/cse_telemetry.c M src/soc/intel/meteorlake/romstage/romstage.c 5 files changed, 228 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h index d45b112..291a264 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -5,6 +5,8 @@ #if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1) #include "cse_telemetry_v1.h" +#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2) +#include "cse_telemetry_v2.h" #endif #endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h new file mode 100644 index 0000000..4acdc31 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H + +enum cse_boot_perf_data_v2 { + /* CSME ROM start execution */ + PERF_DATA_CSME_ROM_START = 0, + + /* EC Boot Load Done (CSME ROM starts main execution) */ + PERF_DATA_EC_BOOT_LOAD_DONE = 1, + + /* CSME ROM completed execution / CSME RBE started */ + PERF_DATA_CSME_ROM_COMPLETED = 2, + + /* CSME got ESE Init Done indication from ESE */ + PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, + + /* CSME RBE started SOC.PMC patch and payloads read from SPI flash */ + PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4, + + /* CSME RBE completed SOC.PMC patch and payloads read from SPI flash */ + PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_COMPLETED = 5, + + /* CSME RBE started pushing SOC.PMC patch and payloads */ + PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_START = 6, + + /* CSME RBE completed pushing SOC.PMC patch and payloads */ + PERF_DATA_CSME_RBE_SOC_PMC_PATCH_PUSH_COMPLETED = 7, + + /* CSME RBE set "Boot Stall Done" indication to SOC.PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 8, + + /* CSME RBE Started load IOE.PMC patch and payloads */ + PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_START = 9, + + /* CSME RBE completed to load IOE.PMC patch and payloads */ + PERF_DATA_CSME_RBE_IOE_PMC_PATCH_LOADING_COMPLETED = 10, + + /* CSME RBE jumped to CSME Kernel */ + PERF_DATA_CSME_RBE_KERNEL_JUMP = 11, + + /* CSME BUP start running */ + PERF_DATA_CSME_BUP_START = 12, + + /* CSME established IPC channel communication with ESE */ + PERF_DATA_CSME_IPC_CHANNEL_FOR_ESE_UP = 13, + + /* ESE FW initialization completed */ + PERF_DATA_ESE_FW_INIT_DONE = 14, + + /* PMC set PPS */ + PERF_DATA_PMC_SET_PPS = 15, + + /* CSME got ICC_CFG_START message from PMC */ + PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 16, + + /* PMC got PCH_PWROK */ + PERF_DATA_PMC_GOT_PCH_PWROK = 17, + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 18, + + /* CSME starts PHYs loading - phase 1 - USB, PCIe */ + PERF_DATA_CSME_PHASE1_PHY_LOADING_START = 19, + + /* CSME completed phase 1 PHYs loading - USB, PCIe */ + PERF_DATA_CSME_PHASE1_PHY_LOADING_COMPLETED = 20, + + /* PMC indicated CSME that xxPWRGOOD was asserted */ + PERF_DATA_PMC_PWRGOOD_ASSERTED = 21, + + /* PMC indicated CSME that SYS_PWROK was asserted */ + PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22, + + /* ESE sent IPC message to CSME indicating PUnit load completed */ + PERF_DATA_ESE_PUNIT_LOAD_COMPLETED = 23, + + /* PMC indicates CSME that xxPLTRST was de-asserted */ + PERF_DATA_PMC_PLTRST_DEASSERTED = 24, + + /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */ + PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 25, + + /* CSME starts PHYs loading - phase 2 - UFS */ + PERF_DATA_CSME_PHASE2_PHY_LOADING_START = 26, + + /* CSME completed phase 2 PHYs loading - UFS */ + PERF_DATA_CSME_PHASE2_PHY_LOADING_COMPLETED = 27, + + /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */ + PERF_DATA_CSME_CPU_BOOT_CONFIG_DONE = 28, + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 29, + + /* ESE sent IPC message to CSME indicating DMU load completed */ + PERF_DATA_ESE_DMU_LOAD_COMPLETED = 30, + + /* ACM Active indication - ACM started its execution */ + PERF_DATA_ACM_START = 31, + + /* ACM Done indication - ACM completed execution */ + PERF_DATA_ACM_DONE = 32, + + /* BIOS sent "Get_BIOS_Seed" message to CSME */ + PERF_DATA_BIOS_SEED_MSG_RECEIVED = 33, + + /* CSME responded to "Get_BIOS_Seed" message */ + PERF_DATA_BIOS_SEED_MSG_REPLIED = 34, + + /* BIOS sent DRAM Init Done message */ + PERF_DATA_BIOS_DRAM_INIT_DONE = 35, + + /* CSME sent DRAM Init Done message back to BIOS */ + PERF_DATA_CSME_DRAM_INIT_DONE = 36, + + /* CSME started loading TCSS components (IOM, NPHY, TBT) */ + PERF_DATA_CSME_LOAD_TCSS_START = 37, + + /* CSME start loading ACE */ + PERF_DATA_CSME_LOAD_ACE_START = 38, + + /* CSME started loading eDP PHY */ + PERF_DATA_CSME_LOAD_EDP_PHY_START = 39, + + /* CSME completed loading eDP PHY */ + PERF_DATA_CSME_LOAD_EDP_PHY_COMPLETED = 40, + + /* BIOS sent "Core BIOS Done" message to CSME */ + PERF_DATA_BIOS_BIOS_CORE_DONE = 41, + + /* CSME sent "Core BIOS Done" ack message back to BIOS */ + PERF_DATA_CSME_BIOS_CORE_DONE = 42, + + /* BIOS sent "End Of Post" message to CSME */ + PERF_DATA_BIOS_END_OF_POST = 43, + + /* CSME sent "End Of Post" ack message back to BIOS */ + PERF_DATA_CSME_END_OF_POST = 44, + + /* CSME started loading ISH Bringup module */ + PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 45, + + /* CSME completed loading ISH Bringup module */ + PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 46, + + /* CSME started loading ISH Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_START = 47, + + /* CSME completed loading Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 48, + + /* CSME reached Transition Complete */ + PERF_DATA_CSME_TRANSITION_COMPLETE = 49, + + /* 50 - 62 Reserved */ + + /* Timestamp when CSME responded to BupGetBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 63, +}; + +#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_V2_H diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc index 87fb3a3..fd94cda 100644 --- a/src/soc/intel/meteorlake/Makefile.inc +++ b/src/soc/intel/meteorlake/Makefile.inc @@ -21,6 +21,7 @@ bootblock-y += p2sb.c bootblock-y += soc_info.c +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c diff --git a/src/soc/intel/meteorlake/cse_telemetry.c b/src/soc/intel/meteorlake/cse_telemetry.c new file mode 100644 index 0000000..7f5d947a --- /dev/null +++ b/src/soc/intel/meteorlake/cse_telemetry.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/cse.h> +#include <timestamp.h> + +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) +{ + s64 start_stamp; + + if (!ts) { + printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__); + return; + } + + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + timestamp_add(TS_ESE_DMU_LOAD_END, + start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]); +} diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 2df3e11..ebb440c 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -134,6 +134,10 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } + /* Update coreboot timestamp table with CSE timestamps */ + if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) + cse_get_telemetry_data(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Gerrit-Change-Number: 73713 Gerrit-PatchSet: 12 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
by Dinesh Gehlot (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73713 ) Change subject: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Gerrit-Change-Number: 73713 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:08:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Add new "DMU load completed" TS
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74047 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: commonlib: Add new "DMU load completed" TS ...................................................................... commonlib: Add new "DMU load completed" TS 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot to OS, check cbmem -t Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74047 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 4b1001e..d7575e7 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -143,6 +143,7 @@ /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ TS_ME_ROM_START = 990, + TS_ESE_DMU_LOAD_END = 991, /* 1000+ reserved for payloads */ @@ -332,6 +333,7 @@ /* Intel ME continued */ TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), + TS_NAME_DEF(TS_ESE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), /* Depthcharge entry timestamp */ TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"), -- To view, visit https://review.coreboot.org/c/coreboot/+/74047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Gerrit-Change-Number: 74047 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/intel/alderlake: Add support for CSE timestamp data versions
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73712 ) Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions ...................................................................... soc/intel/alderlake: Add support for CSE timestamp data versions CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/cse_telemetry.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h 8 files changed, 202 insertions(+), 127 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1534a54..e588524 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -36,6 +36,7 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 if SOC_INTEL_ALDERLAKE_PCH_P config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n @@ -44,7 +45,6 @@ select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 @@ -59,7 +59,6 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select TPM_GOOGLE_CR50 select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG @@ -70,7 +69,6 @@ select HAVE_SLP_S0_GATE select MEMORY_SODIMM select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_RAPTORLAKE select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 9580419..dbee074 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c diff --git a/src/soc/intel/alderlake/cse_telemetry.c b/src/soc/intel/alderlake/cse_telemetry.c new file mode 100644 index 0000000..8a92a03 --- /dev/null +++ b/src/soc/intel/alderlake/cse_telemetry.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/cse.h> +#include <timestamp.h> + +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) +{ + s64 start_stamp; + + if (!ts) { + printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__); + return; + } + + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); +} diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55c9e79..33d703f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -211,6 +211,20 @@ Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 1 of the CSE timestamp + definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). + +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 2 of the CSE timestamp + definitions, it can be used for Meteor Lake M/P. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default y diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 5f36360..6502be9 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -6,11 +6,11 @@ #define MSEC_TO_USEC(x) (x * 1000) -static void cbmem_inject_telemetry_data(void) +static void process_cse_telemetry_data(void) { struct cse_boot_perf_rsp cse_perf_data; s64 ts[NUM_CSE_BOOT_PERF_DATA] = {0}; - s64 current_time, start_stamp; + s64 current_time; int zero_point_idx = 0; /* @@ -60,17 +60,7 @@ } /* Inject CSME timestamps into the coreboot timestamp table */ - start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; - - timestamp_add(TS_ME_ROM_START, start_stamp); - timestamp_add(TS_ME_BOOT_STALL_END, - start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); - timestamp_add(TS_ME_ICC_CONFIG_START, - start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); - timestamp_add(TS_ME_HOST_BOOT_PREP_END, - start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); - timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, - start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + soc_cbmem_inject_telemetry_data(ts, current_time); } void cse_get_telemetry_data(void) @@ -81,5 +71,5 @@ return; } - cbmem_inject_telemetry_data(); + process_cse_telemetry_data(); } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c87946f..b39ae7f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -3,6 +3,7 @@ #ifndef SOC_INTEL_COMMON_CSE_H #define SOC_INTEL_COMMON_CSE_H +#include <intelblocks/cse_telemetry.h> #include <types.h> #include <vb2_api.h> @@ -210,116 +211,6 @@ CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18, }; -/* Boot performance data */ -enum cse_boot_perf_data { - /* CSME ROM start execution */ - PERF_DATA_CSME_ROM_START = 0, - - /* EC Boot Load Done (CSME ROM starts main execution) */ - PERF_DATA_EC_BOOT_LOAD_DONE = 1, - - /* CSME ROM completed execution / CSME RBE started */ - PERF_DATA_CSME_ROM_COMPLETED = 2, - - /* CSME got ESE Init Done indication from ESE */ - PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, - - /* CSME RBE start PMC patch/es loading */ - PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, - - /* CSME RBE completed PMC patch/es loading */ - PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5, - - /* CSME RBE set "Boot Stall Done" indication to PMC */ - PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, - - /* CSME start poll for PMC PPS register */ - PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7, - - /* PMC set PPS */ - PERF_DATA_PMC_SET_PPS = 8, - - /* CSME BUP start running */ - PERF_DATA_CSME_BUP_START = 9, - - /* CSME set "Host Boot Prep Done" indication to PMC */ - PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10, - - /* CSME starts PHYs loading */ - PERF_DATA_CSME_PHY_LOADING_START = 11, - - /* CSME completed PHYs loading */ - PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12, - - /* PMC indicated CSME that xxPWRGOOD was asserted */ - PERF_DATA_PMC_PWRGOOD_ASSERTED = 13, - - /* PMC indicated CSME that SYS_PWROK was asserted */ - PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14, - - /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */ - PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15, - - /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */ - PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW = 16, - - /* PMC indicated CSME that xxPLTRST was de-asserted */ - PERF_DATA_PMC_PLTRST_DEASSERTED = 17, - - /* PMC indicated CSME that TCO_S0 was asserted */ - PERF_DATA_PMC_TC0_S0_ASSERTED = 18, - - /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ - PERF_DATA_PMC_SENT_CRDA = 19, - - /* ACM Active indication - ACM started its execution */ - PERF_DATA_ACM_START = 20, - - /* ACM Done indication - ACM completed execution */ - PERF_DATA_ACM_DONE = 21, - - /* BIOS sent DRAM Init Done message */ - PERF_DATA_BIOS_DRAM_INIT_DONE = 22, - - /* CSME sent DRAM Init Done message back to BIOS */ - PERF_DATA_CSME_DRAM_INIT_DONE = 23, - - /* CSME completed loading TCSS */ - PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24, - - /* CSME started loading ISH Bringup module */ - PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25, - - /* CSME completed loading ISH Bringup module */ - PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26, - - /* CSME started loading ISH Main module */ - PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27, - - /* CSME completed loading Main module */ - PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28, - - /* BIOS sent "End Of Post" message to CSME */ - PERF_DATA_BIOS_END_OF_POST = 29, - - /* CSME sent "End Of Post" ack message back to BIOS */ - PERF_DATA_CSME_END_OF_POST = 30, - - /* BIOS sent "Core BIOS Done" message to CSME */ - PERF_DATA_BIOS_BIOS_CORE_DONE = 31, - - /* CSME sent "Core BIOS Done" ack message back to BIOS */ - PERF_DATA_CSME_BIOS_CORE_DONE = 32, - - /* CSME reached Firmware Init Done */ - PERF_DATA_CSME_GW_INIT_DONE = 33, - - /* 34 - 62 Reserved */ - - /* Timestamp when CSME responded to BupGetBootData message itself */ - PERF_DATA_CSME_GET_PERF_RESPONSE = 63, -}; - /* CSE boot performance data */ struct cse_boot_perf_rsp { struct mkhi_hdr hdr; @@ -585,6 +476,12 @@ void soc_disable_heci1_using_pcr(void); /* + * Injects CSE timestamps into cbmem timestamp table. SoC code needs to + * implement it since timestamp definitions differ from SoC to SoC. + */ +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time); + +/* * Get all the timestamps CSE collected using cse_get_boot_performance_data() and * insert them into the CBMEM timestamp table. */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h new file mode 100644 index 0000000..d45b112 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_H + +#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1) +#include "cse_telemetry_v1.h" +#endif + +#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h new file mode 100644 index 0000000..d0c8180 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H + +enum cse_boot_perf_data_v1 { + /* CSME ROM start execution */ + PERF_DATA_CSME_ROM_START = 0, + + /* EC Boot Load Done (CSME ROM starts main execution) */ + PERF_DATA_EC_BOOT_LOAD_DONE = 1, + + /* CSME ROM completed execution / CSME RBE started */ + PERF_DATA_CSME_ROM_COMPLETED = 2, + + /* CSME got ESE Init Done indication from ESE */ + PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, + + /* CSME RBE start PMC patch/es loading */ + PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, + + /* CSME RBE completed PMC patch/es loading */ + PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5, + + /* CSME RBE set "Boot Stall Done" indication to PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, + + /* CSME start poll for PMC PPS register */ + PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7, + + /* PMC set PPS */ + PERF_DATA_PMC_SET_PPS = 8, + + /* CSME BUP start running */ + PERF_DATA_CSME_BUP_START = 9, + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10, + + /* CSME starts PHYs loading */ + PERF_DATA_CSME_PHY_LOADING_START = 11, + + /* CSME completed PHYs loading */ + PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12, + + /* PMC indicated CSME that xxPWRGOOD was asserted */ + PERF_DATA_PMC_PWRGOOD_ASSERTED = 13, + + /* PMC indicated CSME that SYS_PWROK was asserted */ + PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14, + + /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */ + PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15, + + /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */ + PERF_DATA_CSME_CPU_BOOT_CONFIG_DONE = 16, + + /* PMC indicated CSME that xxPLTRST was de-asserted */ + PERF_DATA_PMC_PLTRST_DEASSERTED = 17, + + /* PMC indicated CSME that TCO_S0 was asserted */ + PERF_DATA_PMC_TC0_S0_ASSERTED = 18, + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 19, + + /* ACM Active indication - ACM started its execution */ + PERF_DATA_ACM_START = 20, + + /* ACM Done indication - ACM completed execution */ + PERF_DATA_ACM_DONE = 21, + + /* BIOS sent DRAM Init Done message */ + PERF_DATA_BIOS_DRAM_INIT_DONE = 22, + + /* CSME sent DRAM Init Done message back to BIOS */ + PERF_DATA_CSME_DRAM_INIT_DONE = 23, + + /* CSME completed loading TCSS */ + PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24, + + /* CSME started loading ISH Bringup module */ + PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25, + + /* CSME completed loading ISH Bringup module */ + PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26, + + /* CSME started loading ISH Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27, + + /* CSME completed loading Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28, + + /* BIOS sent "End Of Post" message to CSME */ + PERF_DATA_BIOS_END_OF_POST = 29, + + /* CSME sent "End Of Post" ack message back to BIOS */ + PERF_DATA_CSME_END_OF_POST = 30, + + /* BIOS sent "Core BIOS Done" message to CSME */ + PERF_DATA_BIOS_BIOS_CORE_DONE = 31, + + /* CSME sent "Core BIOS Done" ack message back to BIOS */ + PERF_DATA_CSME_BIOS_CORE_DONE = 32, + + /* CSME reached Firmware Init Done */ + PERF_DATA_CSME_GW_INIT_DONE = 33, + + /* 34 - 62 Reserved */ + + /* Timestamp when CSME responded to BupGetBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 63, +}; + +#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H -- To view, visit https://review.coreboot.org/c/coreboot/+/73712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Gerrit-Change-Number: 73712 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: soc/intel/alderlake: Add support for CSE timestamp data versions
by Dinesh Gehlot (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Wonkyu Kim, Paul Menzel. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73712 ) Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Gerrit-Change-Number: 73712 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:07:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Stefan Ott, Bill XIE, Alexander Couzens. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74181 ) Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Gerrit-Change-Number: 74181 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:06:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value()
by Arthur Heymans (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Bill XIE. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74179 ) Change subject: nb/intel/gm45: Prevent null-deref in get_blc_pwm_freq_value() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5 Gerrit-Change-Number: 74179 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Tue, 04 Apr 2023 08:06:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023