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Change subject: soc/intel/cmn/pcie: Add ability for SoC to overwrite snoop/no-snoop latency
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74141/comment/b7af75aa_88cedd14
PS4, Line 7: Add ability for
Allow
https://review.coreboot.org/c/coreboot/+/74141/comment/6c7adc54_21899401
PS4, Line 9: require
requires
https://review.coreboot.org/c/coreboot/+/74141/comment/674437e7_48f52ad4
PS4, Line 10: tolerance, let it overwrite the common code settings.
… in devicetree? Kconfig?
File src/soc/intel/common/block/pcie/pcie.c:
https://review.coreboot.org/c/coreboot/+/74141/comment/21405c96_4fbf4816
PS4, Line 14: __weak
I think, coreboot tries to avoid weak functions.
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Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74075/comment/8c865839_46e36f20
PS4, Line 10: updated
update
https://review.coreboot.org/c/coreboot/+/74075/comment/6356e3db_708d14cc
PS4, Line 12: Builds
and boots
https://review.coreboot.org/c/coreboot/+/74075/comment/eff27e05_a04058a6
PS4, Line 12: TEST: Builds, the device enumerates.
Maybe paste the log line from coreboot.
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Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz
......................................................................
mb/lenovo/x200/blc: Add LTN121AT07L02 at 750Hz
The vendor sets BLC_PWM_CTL to 0x31313131.
This value seems working well on the x200 with this panel, which is
said to be LED.
Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
---
M src/mainboard/lenovo/x200/blc.c
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/74182/6
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Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens,
I'd like you to reexamine a change. Please visit
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Change subject: mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
......................................................................
mb/lenovo/x200: Read EDID in mainboard_vbt_filename()
mainboard_vbt_filename() used to assume that it is called after a call
to get_blc_pwm_freq_value() with a valid parameter, but currently it
is the first call of get_blc_pwm_freq_value(NULL), and will return 0,
making "data_led.vbt" is always returned, regardless of the actual
type of the panel.
Combined with the previous commit, in this commit
mainboard_vbt_filename() will explicitly read EDID string via
get_edid_str() and use this string to call get_blc_pwm_freq_value().
This will resolve https://ticket.coreboot.org/issues/475 .
Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB
(CCFL).
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4
---
M src/mainboard/lenovo/x200/blc.c
1 file changed, 28 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74181/5
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Change subject: mb/google/rex: Add DTT thermal settings for policies
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/rex/variants/rex0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71166/comment/e8f87530_7e167a65
PS5, Line 129: # TODO: below values are initial reference values only
can u please keep a bug open for tracking purpose and add here as `FIXME`?
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Change subject: mb/google/rex: Add DTT thermal settings for policies
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71166/comment/a4eec443_3193bcbc
PS5, Line 13: =Built and tested on Rex board
wondering if u can add more specific test details to support this work?
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Change subject: nb/intel/gm45: Export EDID-reading routine as a function
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/intel/gm45/gma.c:
https://review.coreboot.org/c/coreboot/+/74180/comment/3f8d94e4_ef0a579f
PS2, Line 161: /*
: * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M
: * cycles are simply not decoded which is fine.
: */
: pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
: memset(mmio + 2 * MiB, 0, 2 * MiB);
> Should it be moved into gma_func0_init()?
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: nb/intel/gm45: Export EDID-reading routine as a function
......................................................................
nb/intel/gm45: Export EDID-reading routine as a function
It will cache decoded EDID string in a static array. If called more
than once, a pointer to the static array is directly returned, without
reading EDID again.
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca
---
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/gma.c
2 files changed, 47 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/74180/3
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