coreboot-gerrit April 2023

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[S] Change in coreboot[master]: arch/x86/smbios: Check str for NULL in smbios_add_string()
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73980 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86/smbios: Check str for NULL in smbios_add_string() ...................................................................... arch/x86/smbios: Check str for NULL in smbios_add_string() Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73980 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/arch/x86/smbios.c 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 188fb42..1ec0ad2 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -45,7 +45,7 @@ * Return 0 as required for empty strings. * See Section 6.1.3 "Text Strings" of the SMBIOS specification. */ - if (*str == '\0') + if (str == NULL || *str == '\0') return 0; for (;;) { -- To view, visit https://review.coreboot.org/c/coreboot/+/73980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Gerrit-Change-Number: 73980 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program
by Subrata Banik (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Paul Menzel, Ivy Jian, Eric Lai, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/cpu.c: https://review.coreboot.org/c/coreboot/+/74161/comment/3cee9863_1dd192f9 PS4, Line 150: conf > It doesn't exist on ToT. > `const config_t *conf = config_of_soc();` line number #128? that CL has landed today. -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:21:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Maciej Pijanowski (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Michał Żygowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 9: (14 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73934/comment/7c841cf4_42dc4c32 PS9, Line 10: Documents: Intel Datasheet: 633935, rev. 006 Document number needs to be fixed File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/217a95ea_0ac4abb7 PS9, Line 140: const char *const jasperlake_pch_community1_sys_names[] = { For example, ADL-P defines almost the same group as: "alderlake_pch_p_group_hvcmos_names". Please consult with both datasheets to see if we can come up with a better name. https://review.coreboot.org/c/coreboot/+/73934/comment/1ab79bd0_31261e4d PS9, Line 190: const char *const jasperlake_pch_community1_jtag_names[] = { If you see at others, the naming convention is typically: "emmitsburg_group_jtag ", We can drop the "community1" here. https://review.coreboot.org/c/coreboot/+/73934/comment/6815f62a_10ca95b6 PS9, Line 203: .display = "------- GPIO Group GPP_SYS_JTAG -------", As far as I can see, others uarchs typically use: "------- GPIO Group JTAG -------" https://review.coreboot.org/c/coreboot/+/73934/comment/70119c4a_5d6b4de5 PS9, Line 281: "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", This can probably be included in a group. See alderlake_p.h for example, as a reference. https://review.coreboot.org/c/coreboot/+/73934/comment/675d3059_aeea8423 PS9, Line 292: const char *const jasperlake_pch_group_spi0_names[] = { "jasperlake_pch_group_spi_names" should be enough https://review.coreboot.org/c/coreboot/+/73934/comment/099fce75_2454f1eb PS9, Line 305: .display = "------- GPIO Group GPP_H -------", This should be: "------- GPIO Group SPI -------" https://review.coreboot.org/c/coreboot/+/73934/comment/2b00749b_adab7986 PS9, Line 312: "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", Another instance that can probably be included in already existing group, and this group can be then removed. https://review.coreboot.org/c/coreboot/+/73934/comment/7f54e21d_a3369f15 PS9, Line 317: .display = "------- GPIO Group GPP_B -------", The display name is incorrect, but it will be gone once we merge loopbacks into some group. https://review.coreboot.org/c/coreboot/+/73934/comment/1b77bd7c_15274232 PS9, Line 359: const char *const jasperlake_pch_group_sys_comm2_names[] = { This should be "jasperlake_pch_group_cpu_names". Consult alderlake_h.h as an example. https://review.coreboot.org/c/coreboot/+/73934/comment/368df303_55d1705f PS9, Line 378: .display = "------- GPIO Group GPP_SYS_COMM2 -------", "------- GPIO Group CPU -------" https://review.coreboot.org/c/coreboot/+/73934/comment/cd17fc26_e180fe2f PS9, Line 384: const char *const jasperlake_pch_group_sys_pcie_names[] = { "jasperlake_pch_group_pcie_vgpio_names" fits probably better https://review.coreboot.org/c/coreboot/+/73934/comment/59757cab_a0c43b31 PS9, Line 467: .display = "------- GPIO Group GPP_SYS_PCIE -------", "------- GPIO Group PCIe vGPIO -------" https://review.coreboot.org/c/coreboot/+/73934/comment/e2d60a1d_81774e4d PS9, Line 473: const char *const jasperlake_pch_group_sys_vusb_names[] = { maybe "jasperlake_pch_group_vgpio_usb_names", or similar -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 9 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:19:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/myst: Add new mainboard
by Eric Lai (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Raul Rangel, Martin L Roth, Jon Murphy, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Felix Held, Mark Hasemeyer. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74093 ) Change subject: mb/google/myst: Add new mainboard ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/myst/dsdt.asl: https://review.coreboot.org/c/coreboot/+/74093/comment/3e93a6bf_166686f6 PS2, Line 16: Name(LIDS, 0) > i'd say that it would be good if that was moved to the EC's acpi code to which this belongs, but tha […] I didn't see who use this in AMD SoC code. And this is in chrome EC LID device code. https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… Do we still need this? -- To view, visit https://review.coreboot.org/c/coreboot/+/74093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Gerrit-Change-Number: 74093 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:08:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Hide unused GPP port
by Eric Lai (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Martin L Roth, Jason Nien, Karthik Ramasubramanian, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73862 ) Change subject: mb/google/skyrim: Hide unused GPP port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/73862/comment/be073420_32c1be97 PS1, Line 110: device ref gpp_bridge_3 hidden end > I don't know what you mean by 'overlap'. […] oh, I see it's the FSP different. So if we have 4 lane SSD for example, we need hidden 3 GPP ports? -- To view, visit https://review.coreboot.org/c/coreboot/+/73862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c1e4c21649610b856469b164ce5b0221f01b7f9 Gerrit-Change-Number: 73862 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Apr 2023 13:02:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Maciej Pijanowski (Code Review) 04 Apr '23

04 Apr '23

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program
by Kapil Porwal (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Paul Menzel, Ivy Jian, Eric Lai, Ronak Kanabar. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/meteorlake/cpu.c: https://review.coreboot.org/c/coreboot/+/74161/comment/30b91926_b4d57ae0 PS4, Line 150: conf It doesn't exist on ToT. `const config_t *conf = config_of_soc();` -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Tue, 04 Apr 2023 12:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74075 ) Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74075/comment/e4c83958_0d6c5f4e PS4, Line 10: updated > update Done https://review.coreboot.org/c/coreboot/+/74075/comment/fd93e796_032ea76e PS4, Line 12: TEST: Builds, the device enumerates. > Maybe paste the log line from coreboot. Done https://review.coreboot.org/c/coreboot/+/74075/comment/0cf86064_6b3bf30a PS4, Line 12: Builds > and boots Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 5 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 04 Apr 2023 12:45:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0
by Anand Vaikar (Code Review) 04 Apr '23

04 Apr '23

Attention is currently required from: Jason Glenesk, ritul guru, Anand Vaikar, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Paul Menzel, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74075 to look at the new patch set (#5). Change subject: mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 ...................................................................... mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0 The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence update the correct bridge number in the device tree. TEST: Builds and boots, the device enumerates. [DEBUG] PCI: 00:02.4 [1022/14ee] enabled [DEBUG] PCI: 01:00.0 [144d/a80a] enabled Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 --- M src/mainboard/amd/mayan/devicetree_phoenix.cb 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74075/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Gerrit-Change-Number: 74075 Gerrit-PatchSet: 5 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Remove Soundwire workaround
by Felix Held (Code Review) 04 Apr '23

04 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72669 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl: Remove Soundwire workaround ...................................................................... mb/starlabs/starbook/adl: Remove Soundwire workaround This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/acpi/mainboard.asl 1 file changed, 17 insertions(+), 29 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/acpi/mainboard.asl b/src/mainboard/starlabs/starbook/acpi/mainboard.asl index 5bdde36..34b90af 100644 --- a/src/mainboard/starlabs/starbook/acpi/mainboard.asl +++ b/src/mainboard/starlabs/starbook/acpi/mainboard.asl @@ -3,32 +3,3 @@ Scope (\_SB) { #include "sleep.asl" } - -/* - * This platform doesn't support SoundWire but there - * is a kernel bug in some 5.10.x releases. - * - * Debian testing live CD (at 4th Feb 2021) uses 5.10.9-1. More - * details can be found at https://bit.ly/3ttdffG but it appears to - * be triggered by missing SoundWire ACPI entries. - * - * Add the minimal set to make it work again. - */ -Scope (_SB.PCI0.HDAS) -{ - Device (SNDW) - { - Name (_ADR, 0x40000000) - - Name (_CID, Package (0x02) - { - "PRP0001", - "PNP0A05" - }) - - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Gerrit-Change-Number: 72669 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit April 2023