coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#14). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 699 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 14 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski. Karol Zmyslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73934 ) Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... Patch Set 12: (16 comments) File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/b98321cd_0f3e5f7f PS12, Line 8: const char *const jasperlake_pch_group_a_names[] = { > This group is not used in any of the communities. Done. Corrected, it is already in community_5 https://review.coreboot.org/c/coreboot/+/73934/comment/76f4a9b4_07e49004 PS12, Line 28: "GPP_A19", "PCHHOT_N", "n/a", > After A19, we have ESPI_CLK_LOOPBK in datasheet Done https://review.coreboot.org/c/coreboot/+/73934/comment/8ace1eb9_3b830d4f PS12, Line 63: > Please remove empty line Done https://review.coreboot.org/c/coreboot/+/73934/comment/2490bd97_56958421 PS12, Line 64: "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", "n/a", > Inconsistent indents in this group after adding LOOBPKG entries Done https://review.coreboot.org/c/coreboot/+/73934/comment/807e3680_32180de7 PS12, Line 214: "GPP_F04", "CNV_RF_RESET_N", > Can you explain, why do we start from F04? In datasheet I can see it starts from F00. Done. I could not find NF1 for this pad, so currently, I left "n/a". https://review.coreboot.org/c/coreboot/+/73934/comment/cacb30c5_dfd1c935 PS12, Line 226: "GPP_F18", "EMMC_RESET_N", > Can you explain, why do we stop at F18? In datasheet I can see F19 as well. Done, but I could not find NF1 for this pad. https://review.coreboot.org/c/coreboot/+/73934/comment/11b40297_7bf31f1f PS12, Line 274: "GPP_H19", "n/a", "n/a", "n/a", > Don't we have up to H23 in datasheet? Done https://review.coreboot.org/c/coreboot/+/73934/comment/f6f9be5a_e7624200 PS12, Line 308: const struct gpio_group jasperlake_pch_group_spi0 = { > We have "jasperlake_pch_group_spi_names` but group is called: "jasperlake_pch_group_spi0"... […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/048e19f8_fca5d52c PS12, Line 458: const struct gpio_group jasperlake_pch_group_sys_pcie = { > Again, lack of consistency... […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/824deb50_0b56a641 PS12, Line 480: const struct gpio_group jasperlake_pch_group_sys_vusb = { > Change to: "jasperlake_pch_group_vgpio_usb" Done https://review.coreboot.org/c/coreboot/+/73934/comment/cabbc635_2b702b81 PS12, Line 539: // Deep Sleep Well group > Not sure how relevant this comment is. […] Done https://review.coreboot.org/c/coreboot/+/73934/comment/8b14c4f2_f44db641 PS12, Line 552: > Why empty line? Just for visibility. So, I will remove it. https://review.coreboot.org/c/coreboot/+/73934/comment/00a888e2_aa0e47de PS12, Line 584: > Sometimes 0, sometimes 1, sometimes 2 empty lines after this comment... This is mess. […] Only for reference with original Intel documentation. Currently, it's a helper comment. https://review.coreboot.org/c/coreboot/+/73934/comment/11a558c3_d2281f7f PS12, Line 657: &jasperlake_pch_group_b, > group_a is missing after group_b in this community Done https://review.coreboot.org/c/coreboot/+/73934/comment/8da821a7_e8cfbf61 PS12, Line 660: > empty line? Done File util/inteltool/gpio_names/jasperlake.h: https://review.coreboot.org/c/coreboot/+/73934/comment/da7c9fbe_eff6e9e9 PS9, Line 281: "GSPI2_CLK_LOOPBK", "GSPI2_CLK_LOOPBK", > Again, it is still not changed. It should go to group D, if I see correctly. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 12 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 09:08:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/inteltool: Add support for Jasper Lake
by Karol Zmyslowski (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Michał Żygowski, Jakub Czapiga, Karol Zmyslowski, Stefan Reinauer, Michal Zygowski. Hello build bot (Jenkins), Maciej Pijanowski, Jakub Czapiga, Stefan Reinauer, Michal Zygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73934 to look at the new patch set (#13). Change subject: util/inteltool: Add support for Jasper Lake ...................................................................... util/inteltool: Add support for Jasper Lake Tested on: GW-R86S-P1 Documents: Intel Datasheet: 634545, rev. 001 Document Number: Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski(a)3mdeb.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c A util/inteltool/gpio_names/jasperlake.h M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/pcr.c 6 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/73934/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/73934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Gerrit-Change-Number: 73934 Gerrit-PatchSet: 13 Gerrit-Owner: Karol Zmyslowski Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Karol Zmyslowski Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin. jason-ch chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74062 ) Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74062/comment/2eab8f7a_cb14b34f PS4, Line 9: Use the same method for memory saving to be consistent with other : projects. The initial 1480 bytes of the GPIO driving array were : downsized to 24 bytes. : > Create a new GPIO driving info table that contains only the pins used in the bootblock. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 09:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74064 to look at the new patch set (#8). Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR ...................................................................... soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.8 and 5.19 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 [DEBUG] mtk_snfc_init: got pin drive: 0x3 Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/spi.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74064/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/74064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b Gerrit-Change-Number: 74064 Gerrit-PatchSet: 8 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/mediatek/mt8188: Add GPIO driving functions
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74063 to look at the new patch set (#8). Change subject: soc/mediatek/mt8188: Add GPIO driving functions ...................................................................... soc/mediatek/mt8188: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. This implementation is according to chapter 5.2 in MT8188 Functional Specification. BUG=b:270911452 TEST=build pass Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/mt8188/gpio.c 1 file changed, 265 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74063/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/74063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87cb8dc00c90fd5b3c0b8bdf5acb92b6f7393a73 Gerrit-Change-Number: 74063 Gerrit-PatchSet: 8 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/mediatek/mt8186: Move GPIO driving-related functions to common
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74068 to look at the new patch set (#5). Change subject: soc/mediatek/mt8186: Move GPIO driving-related functions to common ...................................................................... soc/mediatek/mt8186: Move GPIO driving-related functions to common Move GPIO driving-related functions to common for code reuse. BUG=b:270911452 TEST=build pass Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h M src/soc/mediatek/mt8188/include/soc/gpio.h 5 files changed, 138 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74068/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I234a2b7ef5075313144a930332bed10ffec00c6c Gerrit-Change-Number: 74068 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by jason-ch chen (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74062 to look at the new patch set (#5). Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... soc/mediatek/mt8186: Reduce GPIO code size in bootblock Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downloaded from 1480 bytes to 24 bytes. BUG=b:270911452 TEST=build pass Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 122 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74062/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
by Yidi Lin (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Hung-Te Lin, jason-ch chen, Paul Menzel. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74062 ) Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74062/comment/297702b3_b50f557f PS4, Line 9: Use the same method for memory saving to be consistent with other : projects. The initial 1480 bytes of the GPIO driving array were : downsized to 24 bytes. : Create a new GPIO driving info table that contains only the pins used in the bootblock. The GPIO driving info table is downloaded from 1480 bytes to 24 bytes. -- To view, visit https://review.coreboot.org/c/coreboot/+/74062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a Gerrit-Change-Number: 74062 Gerrit-PatchSet: 4 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 06 Apr 2023 08:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/ibm: Add 4 SPR sockets server board IBM SBP1
by Patrick Rudolph (Code Review) 06 Apr '23

06 Apr '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, David Hendricks, Angel Pons, Shuo Liu, Nill Ge. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1 ...................................................................... Patch Set 10: (1 comment) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/6759a792_1a585223 PS9, Line 31: MAX_SOCKET_UPD > Why are there two Kconfigs? The soc code has two Kconfigs. Please refer to the soc code authors for design related questions. -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Comment-Date: Thu, 06 Apr 2023 08:37:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2023