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Change subject: soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytes
......................................................................
soc/mediatek/mt8188: Reduce lastbus configuration size by 1280 bytes
Original lastbus configuration consumes constant memory size by
allocating 16 and 8 members arrays and the utilization is bad. Refactor
the lastbus structs to save memory usage.
BRANCH=none
BUG=none
TEST=bootblock.raw.bin size is reduced from 60328 bytes to 59048 bytes.
Change-Id: I07ff9ff7c75f03219e1792b92b62814293ef43fe
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/soc/mediatek/common/include/soc/lastbus_v2.h
M src/soc/mediatek/mt8188/lastbus.c
2 files changed, 95 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74061/3
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Change subject: soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
......................................................................
soc/mediatek/mt8188: Set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.8 and 5.19 in MT8188
Functional Specification.
BUG=b:270911452
TEST=build pass
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
[DEBUG] mtk_snfc_init: got pin drive: 0x3
Change-Id: If8344449f5b34cefcaaee6936e94f7f669c7148b
Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com>
---
M src/soc/mediatek/mt8188/spi.c
1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/74064/7
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Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, Yidi Lin,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8186: Reduce GPIO code size in bootblock
......................................................................
soc/mediatek/mt8186: Reduce GPIO code size in bootblock
Use the same method for memory saving to be consistent with other
projects. The initial 1480 bytes of the GPIO driving array were
downsized to 24 bytes.
BUG=b:270911452
TEST=build pass
Change-Id: I24775ba93cd74ae401747c2f5a26bbf1c8f6ac0a
Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com>
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 122 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74062/4
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/block/cse: Implement an API to get ISH version
......................................................................
soc/intel/cmn/block/cse: Implement an API to get ISH version
This patch adds an API that will fetch the current ISH version from
cbmem. It alerts the user if the current ISH version is outdated.
BUG=b:273661726
Test=The ISHC version, 5.4.2.7779, was retrieved on the Nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ib3f983d5de5b169474bcdb1e9e2934174a9dadf8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74209/5
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Hello build bot (Jenkins), SRIDHAR SIRICILLA, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Rizwan Qureshi, Reka Norman, Kapil Porwal, Meera Ravindranath,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details
......................................................................
soc/intel/cmd/block: Implement an API to get firmware partition details
This patch retrieves details of a specified firmware partition. The
information retrieved includes the mkhi header, current firmware
version, and other information about the partition. The patch
communicates with the ME using the HECI command to acquire this
information.
BUG=b:273661726
Test=Verified the changes for ISHC partition on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/17
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Change subject: soc/intel/cmn/block/cse: Implement an API to get ISH version
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/a5040248_17f20f11
PS4, Line 1221: #if ENV_RAMSTAGE
keep everything inside same #if ENV_RAMSTAGE at line 1267
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Change subject: soc/intel/cmn/block/cse: Implement an API to get ISH version
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/74209/comment/b4c0657c_40965663
PS4, Line 1216: /*
: * This API can only be executed after FSP-M has been initialized. This is because the
: * command relies on resources that are not available until CSE DRAM initialization
: * command has been sent.
: */
Give one space to start with, here is some sample style which u can follow.
```
/*
* Initialize the CSE device with provided temporary BAR. If BAR is 0 use a
* default. This is intended for pre-mem usage only where BARs haven't been
* assigned yet and devices are not enabled.
*/
```
https://review.coreboot.org/c/coreboot/+/74209/comment/385edbcf_edc92452
PS4, Line 1227: sizeof(struct fw_version)
use directly in line #1229
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Ron Lee,
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Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
......................................................................
mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815
retimer on USB U1/U2 transition. The usb_lpm_incapable config is
used to disable USB U1/U2 transition for these Type-C ports.
BUG=b:277149723
BRANCH=firmware-brya-14505.B
TEST=Plug in device and check LPM sysfs nodes are disabled
localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u1
disabled
localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u2
disabled
Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/omnigul/overridetree.cb
1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/74246/3
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Change subject: mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C port
......................................................................
Patch Set 2:
This change is ready for review.
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