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Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74061 )
Change subject: soc/mediatek/mt8188: Reduce lastbus configuration size
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74061/comment/4ca22226_d545ba93
PS2, Line 10: memory
> Do you mean memory or flash ROM size?
After adding GPIO driving support, bootlock exceeds its allocated memory size(60K).
https://review.coreboot.org/c/coreboot/+/74061/comment/f945ae30_825be2cb
PS2, Line 13: BUG=none
> I thought all Chromium change-sets need an issue?
No, this patch is picked to `GPIO driving` patchset to solve the compilation failure.
https://review.coreboot.org/c/coreboot/+/74061/comment/80ca6a6e_81adcc81
PS2, Line 15:
> Isn’t the bootblock compressed? How big is the difference in CBFS?
No, the bootblock is not compressed.
bootblock.bin equals bootblock.raw.bin with SoC specific header.
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74184 )
Change subject: soc/intel/xeon_sp/spr: Default to X2APIC support
......................................................................
soc/intel/xeon_sp/spr: Default to X2APIC support
When more than 255 CPU cores are present on a board
the X2APIC must be used.
Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.
Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
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Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 7aa1fec..832aab5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -8,6 +8,7 @@
select SAVE_MRC_AFTER_FSPS
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select DISABLE_ACPI_HIBERNATE
+ select DEFAULT_X2APIC_RUNTIME
config CHIPSET_DEVICETREE
string
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Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Paul Menzel, Ziang Wang, Christian Walter, Arthur Heymans, Lean Sheng Tan, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74231
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp/acpi: Fix _OSC method
......................................................................
soc/intel/xeon_sp/acpi: Fix _OSC method
Fix a couple of bugs in the _OSC method for handling
"PCI Host Bridge Device" on Xeon-SP.
- Drop the Sleep. The code doesn't write to hardware at all, so
there's no need to sleep here.
- Make sure that the number of DWORD passed in Arg2 is at least 3.
The existing check was useless as it would not create the
DWordField, but then use it anyways.
- Add check for CXL 2 device method calls which provide a 5 DWORD
long buffer to prevent buffer overflows when invoking the
"PCI Host Bridge Device" method.
Test:
Boot on Archer City and confirm that no ACPI errors are reported
for _OSC.
Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
3 files changed, 55 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/74231/3
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Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 )
Change subject: soc/intel/common: Order the different types of cores based on APIC IDs
......................................................................
Patch Set 18:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72132/comment/ce0dd406_10aac47e
PS18, Line 13: /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
> Hey, no problem, you can ask questions. […]
OK, thank you for the explanation - all clear. In my case, the test was conducted on a RPL-P, where probably, as you say, the cores are already sorted starting from P-Cores as with ADL.
Nevertheless, could possibly we see this patch having an affect on MTL core ordering then?
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Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74057 )
Change subject: configs/config.amd_mayan: Add defconfig file for Mayan board
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74057/comment/50a71573_f39abf86
PS2, Line 8:
> Hmm, then it’s getting build tested already as far as I know. […]
yes, some of the config values we have introduced in config file are not same as the Kconfig default value.
Example below :
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_VGA_BIOS=y
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John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74087 )
Change subject: mb/google/skyrim: Enable UPD usb3_port_force_gen1 for Markarth
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/skyrim/variants/markarth/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/74087/comment/ab1e2938_b7bd5f48
PS1, Line 15:
> just to confirm, Markarth will force all type-c to gen1,or all usb3.0 ports? […]
From request, limit all type-C port to Gen1 on Markarth.
I was updated CL for this setting and also check to use "lsusb -t" on my DUT.
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Change subject: soc/intel/xeon_sp/spr: Update dsdt stack status on socket presence
......................................................................
Abandoned
duplicate of 74183
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